From cbb8d8ad24cf356d67f8f3a29014342252b9a5b1 Mon Sep 17 00:00:00 2001 From: Corey Osgood Date: Tue, 19 Jun 2007 07:33:39 +0000 Subject: This patch fixes up a couple mistakes I made with the i82810 and mew-vw to make the system boot to a command line. This patch comments out the code to set up the vga framebuffer to allow the system to boot, without this fix the system hangs during elfboot. The only line that is absolutely necessary to change is the SMRAM setup, however I've commented out all vga setup to make it very obvious to both the kernel/payload and anyone looking at the code that vga isn't currently working. This setup might also be better handled in northbridge.c, if it doesn't need to be done before ram init, yet another reason to comment it all. In the future, LinuxBIOS needs to be told that the graphics memory area, 1mb or 512kb (at the user or developer's option), is reserved for the onchip vga, but I'm not sure if it's taken at the top or bottom of the memory, yet. LB may also need to set a base address for the AGP aperture and/or be told that range is reserved as well, whether this was originally the job of the system bios or vga bios is still a mystery. It also corrects the number of entries in irq_tables.c, without this fix the kernel would probably complain and hang due to unmapped IRQs. Signed-off-by: Corey Osgood Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/northbridge/intel/i82810/raminit.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index 55102dbba6..8ebb25f89c 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -69,7 +69,6 @@ SDRAM configuration functions. static void do_ram_command(const struct mem_controller *ctrl, uint32_t command, uint32_t addr_offset, uint32_t row_offset) { - int i; uint8_t reg; /* TODO: Support for multiple DIMMs. */ @@ -242,22 +241,25 @@ static void sdram_set_registers(const struct mem_controller *ctrl) */ /* Ideally, this should be R/W for as many ranges as possible. */ - pci_write_config8(ctrl->d0, PAM, 0x00); + pci_write_config8(ctrl->d0, PAM, 0xff); + /* Enabling the VGA Framebuffer currently screws up the rest of the boot. + * Disable for now */ + /* Enable 1MB framebuffer. */ - pci_write_config8(ctrl->d0, SMRAM, 0xC0); + //pci_write_config8(ctrl->d0, SMRAM, 0xC0); - val = pci_read_config16(ctrl->d0, MISSC); + //val = pci_read_config16(ctrl->d0, MISSC); /* Preserve reserved bits. */ - val &= 0xff06; + //val &= 0xff06; /* Set graphics cache window to 32MB, no power throttling. */ - val |= 0x0001; - pci_write_config16(ctrl->d0, MISSC, val); + //val |= 0x0001; + //pci_write_config16(ctrl->d0, MISSC, val); - val = pci_read_config8(ctrl->d0, MISSC2); + //val = pci_read_config8(ctrl->d0, MISSC2); /* Enable graphics palettes and clock gating (not optional!) */ - val |= 0x06; - pci_write_config8(ctrl->d0, MISSC2, val); + //val |= 0x06; + //pci_write_config8(ctrl->d0, MISSC2, val); } /** -- cgit v1.2.3