From d7bf3ad9397a367021e57d204438a178022aaa8c Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 20:31:39 +0200 Subject: haswell: Compute disabled channel masks at runtime MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All mainboards have a non-zero SPD address to implemented DIMM slots. Knowing this, it is possible to compute the MRC slot population masks automatically instead of hardcoding the values on each mainboard. Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119 Reviewed-by: Tristan Corrick Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/romstage.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index ee211beab1..7c27827921 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -23,6 +23,17 @@ void __weak mb_late_romstage_setup(void) { } +/* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ +static int make_channel_disabled_mask(const struct pei_data *pd, int ch) +{ + return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1); +} + /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { @@ -73,6 +84,10 @@ void mainboard_romstage_entry(void) /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ pei_data.boot_mode = wake_from_s3 ? 2 : 0; + /* Calculate unimplemented DIMM slots for each channel */ + pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); + pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); + timestamp_add_now(TS_BEFORE_INITRAM); report_platform_info(); -- cgit v1.2.3