From df128a55b183d3d7a6d7ae986f33abffac50f371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Sep 2019 18:35:37 +0300 Subject: intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/haswell/haswell.h | 4 --- src/northbridge/intel/i945/early_init.c | 41 ++++++++++++------------- src/northbridge/intel/i945/i945.h | 1 - src/northbridge/intel/nehalem/nehalem.h | 4 --- src/northbridge/intel/pineview/pineview.h | 1 - src/northbridge/intel/sandybridge/sandybridge.h | 4 --- 6 files changed, 20 insertions(+), 35 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 9de0cfb2c3..bd89609601 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -108,10 +108,6 @@ #define GLBIOTLBINV (1 << 1) #define GLBCTXTINV (1 << 0) -/* Device 0:1.0 PCI configuration space (PCI Express) */ - -#define BCTRL1 0x3e /* 16bit */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f9167dfc97..ebff49c6ad 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -546,13 +546,13 @@ static void i945_setup_pci_express_x16(void) */ /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); @@ -610,12 +610,11 @@ static void i945_setup_pci_express_x16(void) reg32 |= 1; pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - - reg16 |= (1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); - reg16 &= ~(1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -663,9 +662,9 @@ static void i945_setup_pci_express_x16(void) pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), BCTRL1); - reg16 |= (1 << 3); - pci_write_config16(PCI_DEV(0, 0x1, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_VGA; + pci_write_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL, reg16); } /* Enable GPEs */ @@ -776,17 +775,17 @@ disable_pciexpress_x16_link: MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 |= (1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 |= (1 << 8); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 &= ~(1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index ebcc8bcb19..d19748eaf9 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -86,7 +86,6 @@ #define SBUSN1 0x19 /* 8bit */ #define SUBUSN1 0x1a /* 8bit */ #define SSTS1 0x1e /* 16bit */ -#define BCTRL1 0x3e /* 16bit */ #define PEG_CAP 0xa2 /* 16bit */ #define DSTS 0xaa /* 16bit */ #define SLOTCAP 0xb4 /* 32bit */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 93024f69d8..21c2a395fe 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -153,10 +153,6 @@ typedef struct { #define SKPAD 0xdc /* Scratchpad Data */ -/* Device 0:1.0 PCI configuration space (PCI Express) */ - -#define BCTRL1 0x3e /* 16bit */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index f53ff17aa3..882f886b21 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -84,7 +84,6 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ -#define BCTRL1 0x3e /* 16bit */ #define PEGSTS 0x214 /* 32bit */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index b598c9b6e9..d505728a3b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -101,10 +101,6 @@ enum platform_type { #define SKPAD 0xdc /* Scratchpad Data */ -/* Device 0:1.0 PCI configuration space (PCI Express) */ - -#define BCTRL1 0x3e /* 16bit */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ -- cgit v1.2.3