From f4cc089f1eb4b8b4a31c4aae63990034f49c5a97 Mon Sep 17 00:00:00 2001
From: Myles Watson <mylesgw@gmail.com>
Date: Wed, 14 Apr 2010 16:50:16 +0000
Subject: Remove few more warnings and some dead code.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/northbridge/amd/amdfam10/amdfam10_acpi.c  | 24 +++++++++++++++++++++++-
 src/northbridge/amd/amdk8/amdk8_acpi.c        | 23 +++++++++++++++++++++++
 src/northbridge/via/vx800/examples/romstage.c |  2 +-
 3 files changed, 47 insertions(+), 2 deletions(-)

(limited to 'src/northbridge')

diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
index ba4c36bee4..7e57cce0ab 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c
@@ -268,6 +268,28 @@ void update_ssdt(void *ssdt)
 
 }
 
+void update_ssdtx(void *ssdtx, int i)
+{
+	u8 *PCI;
+	u8 *HCIN;
+	u8 *UID;
+
+	PCI = ssdtx + 0x32;
+	HCIN = ssdtx + 0x39;
+	UID = ssdtx + 0x40;
+
+	if (i < 7) {
+		*PCI = (u8) ('4' + i - 1);
+	} else {
+		*PCI = (u8) ('A' + i - 1 - 6);
+	}
+	*HCIN = (u8) i;
+	*UID = (u8) (i + 3);
+
+	/* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
 static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex)
 {
 	u8 *CPU;
@@ -291,7 +313,7 @@ static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex)
 	CONTROL = sspr + 0x8d;
 	STATUS = sspr + 0x8f;
 
-	sprintf(CPU, "%02x", (char)cpuindex);
+	sprintf((char*)CPU, "%02x", (char)cpuindex);
 	*CPUIN = (u8) cpuindex;
 
 	for(i=0;i<sysconf.p_state_num;i++) {
diff --git a/src/northbridge/amd/amdk8/amdk8_acpi.c b/src/northbridge/amd/amdk8/amdk8_acpi.c
index 1257f86633..92a4520eac 100644
--- a/src/northbridge/amd/amdk8/amdk8_acpi.c
+++ b/src/northbridge/amd/amdk8/amdk8_acpi.c
@@ -291,3 +291,26 @@ int k8acpi_write_vars(void)
 	acpigen_patch_len(lens - 1);
 	return lens;
 }
+
+void update_ssdtx(void *ssdtx, int i)
+{
+	u8 *PCI;
+	u8 *HCIN;
+	u8 *UID;
+
+	PCI = ssdtx + 0x32;
+	HCIN = ssdtx + 0x39;
+	UID = ssdtx + 0x40;
+
+	if (i < 7) {
+		*PCI = (u8) ('4' + i - 1);
+	} else {
+		*PCI = (u8) ('A' + i - 1 - 6);
+	}
+	*HCIN = (u8) i;
+	*UID = (u8) (i + 3);
+
+	/* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 9fac9a3110..8db60237b7 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -47,7 +47,7 @@
 #include "northbridge/via/vx800/raminit.c"
 
 
-int acpi_is_wakeup_early_via_vx800(void)
+static int acpi_is_wakeup_early_via_vx800(void)
 {
 	device_t dev;
 	u16 tmp, result;
-- 
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