From f7d4f73053f0c26bfe411a9f3ef86f98389538b5 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Sun, 20 Mar 2016 14:21:53 -0500 Subject: nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set Under certain conditions (training abort) BlockRxDqsLock could remain set in violation of the BKDG. Ensure BlockRxDqsLock is reset to 0 after a lane training abort. Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b Reviewed-on: https://review.coreboot.org/14144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Martin Roth --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/northbridge') diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 15b5ea4fcb..5d75fb0392 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1725,6 +1725,12 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, "Training for receiver %d on DCT %d aborted\n", __func__, lane, Receiver, dct); } + + /* Restore BlockRxDqsLock setting to normal operation in preparation for retraining */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8)); + dword &= ~(0x1 << 8); /* BlockRxDqsLock = 0 */ + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword); + break; } -- cgit v1.2.3