From faa5f9869d67ab1a963e1c49afaaf353503586c9 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 4 Jun 2018 19:34:59 +0200 Subject: cpu/intel/haswell: Use the common intel romstage_main function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested on Google peppy (Acer C720). Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/26835 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Kyösti Mälkki --- src/northbridge/intel/haswell/Kconfig | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/northbridge') diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index ae6d81285d..f9c68f34dd 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -58,13 +58,6 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. -config DCACHE_RAM_ROMSTAGE_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage from the data cache - during pre-ram ROM stage execution. - config HAVE_MRC bool "Add a System Agent binary" help -- cgit v1.2.3