From fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 3 Aug 2019 21:28:40 +0300 Subject: northbridge/intel: Rename ram_calc.c to memmap.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/gm45/Makefile.inc | 6 +- src/northbridge/intel/gm45/memmap.c | 166 ++++++++++++++++++++++ src/northbridge/intel/gm45/ram_calc.c | 166 ---------------------- src/northbridge/intel/haswell/Makefile.inc | 6 +- src/northbridge/intel/haswell/memmap.c | 50 +++++++ src/northbridge/intel/haswell/ram_calc.c | 50 ------- src/northbridge/intel/i440bx/Makefile.inc | 6 +- src/northbridge/intel/i440bx/memmap.c | 94 +++++++++++++ src/northbridge/intel/i440bx/ram_calc.c | 94 ------------- src/northbridge/intel/i945/Makefile.inc | 6 +- src/northbridge/intel/i945/memmap.c | 132 ++++++++++++++++++ src/northbridge/intel/i945/ram_calc.c | 132 ------------------ src/northbridge/intel/nehalem/Makefile.inc | 6 +- src/northbridge/intel/nehalem/memmap.c | 89 ++++++++++++ src/northbridge/intel/nehalem/ram_calc.c | 89 ------------ src/northbridge/intel/pineview/Makefile.inc | 6 +- src/northbridge/intel/pineview/memmap.c | 182 +++++++++++++++++++++++++ src/northbridge/intel/pineview/ram_calc.c | 182 ------------------------- src/northbridge/intel/sandybridge/Makefile.inc | 6 +- src/northbridge/intel/sandybridge/memmap.c | 94 +++++++++++++ src/northbridge/intel/sandybridge/ram_calc.c | 94 ------------- src/northbridge/intel/x4x/Makefile.inc | 6 +- src/northbridge/intel/x4x/memmap.c | 177 ++++++++++++++++++++++++ src/northbridge/intel/x4x/ram_calc.c | 177 ------------------------ 24 files changed, 1008 insertions(+), 1008 deletions(-) create mode 100644 src/northbridge/intel/gm45/memmap.c delete mode 100644 src/northbridge/intel/gm45/ram_calc.c create mode 100644 src/northbridge/intel/haswell/memmap.c delete mode 100644 src/northbridge/intel/haswell/ram_calc.c create mode 100644 src/northbridge/intel/i440bx/memmap.c delete mode 100644 src/northbridge/intel/i440bx/ram_calc.c create mode 100644 src/northbridge/intel/i945/memmap.c delete mode 100644 src/northbridge/intel/i945/ram_calc.c create mode 100644 src/northbridge/intel/nehalem/memmap.c delete mode 100644 src/northbridge/intel/nehalem/ram_calc.c create mode 100644 src/northbridge/intel/pineview/memmap.c delete mode 100644 src/northbridge/intel/pineview/ram_calc.c create mode 100644 src/northbridge/intel/sandybridge/memmap.c delete mode 100644 src/northbridge/intel/sandybridge/ram_calc.c create mode 100644 src/northbridge/intel/x4x/memmap.c delete mode 100644 src/northbridge/intel/x4x/ram_calc.c (limited to 'src/northbridge') diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index b59a7c3cd2..0ab1c94a27 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -25,18 +25,18 @@ romstage-y += pcie.c romstage-y += thermal.c romstage-y += igd.c romstage-y += pm.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += iommu.c romstage-y += romstage.c ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c smm-y += ../../../cpu/x86/lapic/apic_timer.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c new file mode 100644 index 0000000000..6795f7a61f --- /dev/null +++ b/src/northbridge/intel/gm45/memmap.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gm45.h" + +/* + * Decodes used Graphics Mode Select (GMS) to kilobytes. + * The options for 1M, 4M, 8M and 16M preallocated igd memory are + * undocumented but are verified to work. + */ +u32 decode_igd_memory_size(const u32 gms) +{ + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, + 96, 160, 224, 352 }; + + if (gms >= ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +} + +/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ +u32 decode_igd_gtt_size(const u32 gsm) +{ + switch (gsm) { + case 0: + return 0 << 10; + case 1: + return 1 << 10; + case 3: + case 9: + return 2 << 10; + case 10: + return 3 << 10; + case 11: + return 4 << 10; + default: + die("Bad Graphics Stolen Memory (GSM) setting.\n"); + return 0; + } +} + +/* Decodes TSEG region size to kilobytes. */ +u32 decode_tseg_size(u8 esmramc) +{ + if (!(esmramc & 1)) + return 0; + switch ((esmramc >> 1) & 3) { + case 0: + return 1 << 10; + case 1: + return 2 << 10; + case 2: + return 8 << 10; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + +u32 northbridge_get_tseg_base(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0, 0); + + u32 tor; + + /* Top of Lower Usable DRAM */ + tor = (pci_read_config16(dev, D0F0_TOLUD) & 0xfff0) << 16; + + /* Graphics memory comes next */ + const u32 ggc = pci_read_config16(dev, D0F0_GGC); + const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); + if (!(ggc & 2)) { + /* Graphics memory */ + tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10; + /* GTT Graphics Stolen Memory Size (GGMS) */ + tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10; + } + /* TSEG size */ + tor -= decode_tseg_size(esmramc) << 10; + return tor; +} + +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + return decode_tseg_size(esmramc) << 10; +} + +/* Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB alignment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ +void *cbmem_top(void) +{ + uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); + return (void *) top_of_ram; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache 8 MiB region below the top of ram and 2 MiB above top of + * ram to cover both cbmem as the TSEG region. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); + + /* We do not return here. */ +} diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c deleted file mode 100644 index 6795f7a61f..0000000000 --- a/src/northbridge/intel/gm45/ram_calc.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "gm45.h" - -/* - * Decodes used Graphics Mode Select (GMS) to kilobytes. - * The options for 1M, 4M, 8M and 16M preallocated igd memory are - * undocumented but are verified to work. - */ -u32 decode_igd_memory_size(const u32 gms) -{ - static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, - 96, 160, 224, 352 }; - - if (gms >= ARRAY_SIZE(ggc2uma)) - die("Bad Graphics Mode Select (GMS) setting.\n"); - - return ggc2uma[gms] << 10; -} - -/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ -u32 decode_igd_gtt_size(const u32 gsm) -{ - switch (gsm) { - case 0: - return 0 << 10; - case 1: - return 1 << 10; - case 3: - case 9: - return 2 << 10; - case 10: - return 3 << 10; - case 11: - return 4 << 10; - default: - die("Bad Graphics Stolen Memory (GSM) setting.\n"); - return 0; - } -} - -/* Decodes TSEG region size to kilobytes. */ -u32 decode_tseg_size(u8 esmramc) -{ - if (!(esmramc & 1)) - return 0; - switch ((esmramc >> 1) & 3) { - case 0: - return 1 << 10; - case 1: - return 2 << 10; - case 2: - return 8 << 10; - case 3: - default: - die("Bad TSEG setting.\n"); - } -} - -u32 northbridge_get_tseg_base(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0, 0); - - u32 tor; - - /* Top of Lower Usable DRAM */ - tor = (pci_read_config16(dev, D0F0_TOLUD) & 0xfff0) << 16; - - /* Graphics memory comes next */ - const u32 ggc = pci_read_config16(dev, D0F0_GGC); - const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC); - if (!(ggc & 2)) { - /* Graphics memory */ - tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10; - /* GTT Graphics Stolen Memory Size (GGMS) */ - tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10; - } - /* TSEG size */ - tor -= decode_tseg_size(esmramc) << 10; - return tor; -} - -u32 northbridge_get_tseg_size(void) -{ - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); - return decode_tseg_size(esmramc) << 10; -} - -/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB alignment. As this may cause very greedy MTRR setup, push - * CBMEM top downwards to 4 MiB boundary. - */ -void *cbmem_top(void) -{ - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; -} - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ -} diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index ca1c04fa13..b9863367c9 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,14 +17,14 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) bootblock-y += bootblock.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c ramstage-y += minihd.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c @@ -37,6 +37,6 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c new file mode 100644 index 0000000000..3a63afcde6 --- /dev/null +++ b/src/northbridge/intel/haswell/memmap.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include "haswell.h" + +static uintptr_t smm_region_start(void) +{ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignment. + */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} + +/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); +} diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c deleted file mode 100644 index 3a63afcde6..0000000000 --- a/src/northbridge/intel/haswell/ram_calc.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include "haswell.h" - -static uintptr_t smm_region_start(void) -{ - /* - * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignment. - */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return tom & ~((1 << 20) - 1); -} - -void *cbmem_top(void) -{ - return (void *)smm_region_start(); -} - -/* Region of SMM space is reserved for multipurpose use. It falls below - * the IED region and above the SMM handler. */ -#define RESERVED_SMM_OFFSET \ - (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE) - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); -} diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index d41f65d755..2c503c63c1 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,12 +17,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c romstage-y += raminit.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c -romstage-y += ram_calc.c +romstage-y += memmap.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c new file mode 100644 index 0000000000..495ca8682a --- /dev/null +++ b/src/northbridge/intel/i440bx/memmap.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Keith Hui + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "i440bx.h" + +void *cbmem_top(void) +{ + /* Base of TSEG is top of usable DRAM */ + /* + * SMRAM - System Management RAM Control Register + * 0x72 + * [7:4] Not relevant to this function. + * [3:3] Global SMRAM Enable (G_SMRAME) + * [2:0] Hardwired to 010. + * + * ESMRAMC - Extended System Management RAM Control + * 0x73 + * [7:7] H_SMRAM_EN + * 1 = When G_SMRAME=1, High SMRAM space is enabled at + * 0x100A0000-0x100FFFFF and forwarded to DRAM address + * 0x000A0000-0x000FFFFF. + * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at + * 0x000A0000-0x000BFFFF. + * [6:3] Not relevant to this function. + * [2:1] TSEG Size (T_SZ) + * Selects the size of the TSEG memory block, if enabled. + * 00 = 128KiB + * 01 = 256KiB + * 10 = 512KiB + * 11 = 1MiB + * [0:0] TSEG_EN + * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to + * appear between DRAM address (TOM-) to TOM. + * + * Source: 440BX datasheet, pages 3-28 thru 3-29. + */ + unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; + + int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; + /* T_SZ and TSEG_EN */ + int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; + if ((tseg & 0x1) && gsmrame) { + int tseg_size = 128 * KiB * (1 << (tseg >> 1)); + tom -= tseg_size; + } + return (void *)tom; +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache CBMEM region as WB. */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); +} diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c deleted file mode 100644 index 495ca8682a..0000000000 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Keith Hui - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "i440bx.h" - -void *cbmem_top(void) -{ - /* Base of TSEG is top of usable DRAM */ - /* - * SMRAM - System Management RAM Control Register - * 0x72 - * [7:4] Not relevant to this function. - * [3:3] Global SMRAM Enable (G_SMRAME) - * [2:0] Hardwired to 010. - * - * ESMRAMC - Extended System Management RAM Control - * 0x73 - * [7:7] H_SMRAM_EN - * 1 = When G_SMRAME=1, High SMRAM space is enabled at - * 0x100A0000-0x100FFFFF and forwarded to DRAM address - * 0x000A0000-0x000FFFFF. - * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at - * 0x000A0000-0x000BFFFF. - * [6:3] Not relevant to this function. - * [2:1] TSEG Size (T_SZ) - * Selects the size of the TSEG memory block, if enabled. - * 00 = 128KiB - * 01 = 256KiB - * 10 = 512KiB - * 11 = 1MiB - * [0:0] TSEG_EN - * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to - * appear between DRAM address (TOM-) to TOM. - * - * Source: 440BX datasheet, pages 3-28 thru 3-29. - */ - unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB; - - int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; - /* T_SZ and TSEG_EN */ - int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; - if ((tseg & 0x1) && gsmrame) { - int tseg_size = 128 * KiB * (1 << (tseg >> 1)); - tom -= tseg_size; - } - return (void *)tom; -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); -} diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index ffeabdc678..47b4c5166b 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -15,12 +15,12 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c @@ -29,6 +29,6 @@ romstage-y += rcven.c smm-y += udelay.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c new file mode 100644 index 0000000000..ac1499e0fc --- /dev/null +++ b/src/northbridge/intel/i945/memmap.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include "i945.h" +#include +#include +#include +#include +#include +#include +#include + +/* Decodes TSEG region size to bytes. */ +u32 decode_tseg_size(const u8 esmramc) +{ + if (!(esmramc & 1)) + return 0; + switch ((esmramc >> 1) & 3) { + case 0: + return 1 << 20; + case 1: + return 2 << 20; + case 2: + return 8 << 20; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + +u32 northbridge_get_tseg_base(void) +{ + uintptr_t tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); + else + tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; + + /* subsctract TSEG size */ + tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); + return tom; +} + +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + return decode_tseg_size(esmramc); +} + +/* + * Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB alignment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ +void *cbmem_top(void) +{ + uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); + return (void *) top_of_ram; +} + +/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +u32 decode_igd_memory_size(const u32 gms) +{ + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, + 48, 64 }; + + if (gms >= ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache 8 MiB region below the top of ram and 2 MiB above top of + * ram to cover both cbmem as the TSEG region. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); + + /* We do not return here. */ +} diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c deleted file mode 100644 index ac1499e0fc..0000000000 --- a/src/northbridge/intel/i945/ram_calc.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include "i945.h" -#include -#include -#include -#include -#include -#include -#include - -/* Decodes TSEG region size to bytes. */ -u32 decode_tseg_size(const u8 esmramc) -{ - if (!(esmramc & 1)) - return 0; - switch ((esmramc >> 1) & 3) { - case 0: - return 1 << 20; - case 1: - return 2 << 20; - case 2: - return 8 << 20; - case 3: - default: - die("Bad TSEG setting.\n"); - } -} - -u32 northbridge_get_tseg_base(void) -{ - uintptr_t tom; - - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) - /* IGD enabled, get top of Memory from BSM register */ - tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); - else - tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; - - /* subsctract TSEG size */ - tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); - return tom; -} - -u32 northbridge_get_tseg_size(void) -{ - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); - return decode_tseg_size(esmramc); -} - -/* - * Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB alignment. As this may cause very greedy MTRR setup, push - * CBMEM top downwards to 4 MiB boundary. - */ -void *cbmem_top(void) -{ - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; -} - -/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ -u32 decode_igd_memory_size(const u32 gms) -{ - static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, - 48, 64 }; - - if (gms >= ARRAY_SIZE(ggc2uma)) - die("Bad Graphics Mode Select (GMS) setting.\n"); - - return ggc2uma[gms] << 10; -} - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ -} diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index c0d46c9a0c..52374acee8 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -15,20 +15,20 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c new file mode 100644 index 0000000000..ec036c9d7c --- /dev/null +++ b/src/northbridge/intel/nehalem/memmap.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google LLC + * Copyright (C) 2013 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "nehalem.h" + +static uintptr_t smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +u32 northbridge_get_tseg_base(void) +{ + return (u32)smm_region_start(); +} + +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); + + /* We do not return here. */ +} diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c deleted file mode 100644 index ec036c9d7c..0000000000 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google LLC - * Copyright (C) 2013 Vladimir Serbinenko. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "nehalem.h" - -static uintptr_t smm_region_start(void) -{ - /* Base of TSEG is top of usable DRAM */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return tom; -} - -u32 northbridge_get_tseg_base(void) -{ - return (u32)smm_region_start(); -} - -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - -void *cbmem_top(void) -{ - return (void *) smm_region_start(); -} - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The stage cache lives at the end of TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() + - northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB - * above top of the ram. This satisfies MTRR alignment requirement - * with different TSEG size configurations. - */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ -} diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index 83487717df..81ee783304 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -19,16 +19,16 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y) bootblock-y += ../../../cpu/x86/early_reset.S bootblock-y += bootblock.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-y += acpi.c romstage-y += romstage.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += raminit.c romstage-y += early_init.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c new file mode 100644 index 0000000000..2f3ff6e921 --- /dev/null +++ b/src/northbridge/intel/pineview/memmap.c @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +u8 decode_pciebar(u32 *const base, u32 *const len) +{ + *base = 0; + *len = 0; + const pci_devfn_t dev = PCI_DEV(0,0,0); + u32 pciexbar = 0; + u32 pciexbar_reg; + u32 reg32; + int max_buses; + const struct { + u16 num_buses; + u32 addr_mask; + } busmask[] = { + {256, 0xf0000000}, + {128, 0xf8000000}, + {64, 0xfc000000}, + {0, 0}, + }; + + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & (1 << 0))) { + printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); + return 0; + } + + reg32 = (pciexbar_reg >> 1) & 3; + pciexbar = pciexbar_reg & busmask[reg32].addr_mask; + max_buses = busmask[reg32].num_buses; + + if (!pciexbar) { + printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); + return 0; + } + + *base = pciexbar; + *len = max_buses << 20; + return 1; +} + +/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +u32 decode_igd_memory_size(const u32 gms) +{ + const u32 gmssize[] = { + 0, 1, 4, 8, 16, 32, 48, 64, 128, 256 + }; + + if (gms > 9) { + printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n"); + return 0; + } + return gmssize[gms] << 10; +} + +/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ +u32 decode_igd_gtt_size(const u32 gsm) +{ + const u8 gsmsize[] = { + 0, 1, 0, 0, + }; + + if (gsm > 3) { + printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n"); + return 0; + } + return (u32)(gsmsize[gsm] << 10); +} + +/** Decodes used TSEG size to bytes. */ +static u32 decode_tseg_size(const u32 esmramc) +{ + if (!(esmramc & 1)) + return 0; + + switch ((esmramc >> 1) & 3) { + case 0: + return 1 << 20; + case 1: + return 2 << 20; + case 2: + return 8 << 20; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + return decode_tseg_size(esmramc); +} + +u32 northbridge_get_tseg_base(void) +{ + return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); +} + + +/* Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB alignment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ +void *cbmem_top(void) +{ + uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); + return (void *) top_of_ram; + +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache 8 MiB region below the top of ram and 2 MiB above top of + * ram to cover both cbmem as the TSEG region. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); + + /* We do not return here. */ +} diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c deleted file mode 100644 index 2f3ff6e921..0000000000 --- a/src/northbridge/intel/pineview/ram_calc.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -u8 decode_pciebar(u32 *const base, u32 *const len) -{ - *base = 0; - *len = 0; - const pci_devfn_t dev = PCI_DEV(0,0,0); - u32 pciexbar = 0; - u32 pciexbar_reg; - u32 reg32; - int max_buses; - const struct { - u16 num_buses; - u32 addr_mask; - } busmask[] = { - {256, 0xf0000000}, - {128, 0xf8000000}, - {64, 0xfc000000}, - {0, 0}, - }; - - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - // MMCFG not supported or not enabled. - if (!(pciexbar_reg & (1 << 0))) { - printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); - return 0; - } - - reg32 = (pciexbar_reg >> 1) & 3; - pciexbar = pciexbar_reg & busmask[reg32].addr_mask; - max_buses = busmask[reg32].num_buses; - - if (!pciexbar) { - printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); - return 0; - } - - *base = pciexbar; - *len = max_buses << 20; - return 1; -} - -/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ -u32 decode_igd_memory_size(const u32 gms) -{ - const u32 gmssize[] = { - 0, 1, 4, 8, 16, 32, 48, 64, 128, 256 - }; - - if (gms > 9) { - printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) value.\n"); - return 0; - } - return gmssize[gms] << 10; -} - -/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */ -u32 decode_igd_gtt_size(const u32 gsm) -{ - const u8 gsmsize[] = { - 0, 1, 0, 0, - }; - - if (gsm > 3) { - printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) value.\n"); - return 0; - } - return (u32)(gsmsize[gsm] << 10); -} - -/** Decodes used TSEG size to bytes. */ -static u32 decode_tseg_size(const u32 esmramc) -{ - if (!(esmramc & 1)) - return 0; - - switch ((esmramc >> 1) & 3) { - case 0: - return 1 << 20; - case 1: - return 2 << 20; - case 2: - return 8 << 20; - case 3: - default: - die("Bad TSEG setting.\n"); - } -} - -u32 northbridge_get_tseg_size(void) -{ - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); - return decode_tseg_size(esmramc); -} - -u32 northbridge_get_tseg_base(void) -{ - return pci_read_config32(PCI_DEV(0, 0, 0), TSEG); -} - - -/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB alignment. As this may cause very greedy MTRR setup, push - * CBMEM top downwards to 4 MiB boundary. - */ -void *cbmem_top(void) -{ - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; - -} - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ -} diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 8a0b67b2c9..77d1fdbb84 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -15,14 +15,14 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE),y) -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += pcie.c ramstage-y += gma.c ramstage-y += acpi.c -romstage-y += ram_calc.c +romstage-y += memmap.c ramstage-y += common.c romstage-y += common.c @@ -48,6 +48,6 @@ romstage-y += ../../../arch/x86/walkcbfs.S smm-y += finalize.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c new file mode 100644 index 0000000000..7d5c173829 --- /dev/null +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sandybridge.h" + +static uintptr_t smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); +} + +u32 northbridge_get_tseg_base(void) +{ + return ALIGN_DOWN(smm_region_start(), 1*MiB); +} + +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size() + - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE); +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + top_of_ram = (uintptr_t)cbmem_top(); + /* Cache 8MiB below the top of ram. On sandybridge systems the top of + * ram under 4GiB is the start of the TSEG region. It is required to + * be 8MiB aligned. Set this area as cacheable so it can be used later + * for ramstage before setting up the entire RAM as cacheable. */ + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + + /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems + * is where the TSEG region resides. However, it is not restricted + * to SMM mode until SMM has been relocated. By setting the region + * to cacheable it provides faster access when relocating the SMM + * handler as well as using the TSEG region for other purposes. */ + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); + + /* We do not return here. */ +} diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c deleted file mode 100644 index 7d5c173829..0000000000 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "sandybridge.h" - -static uintptr_t smm_region_start(void) -{ - /* Base of TSEG is top of usable DRAM */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return tom; -} - -void *cbmem_top(void) -{ - return (void *) smm_region_start(); -} - -u32 northbridge_get_tseg_base(void) -{ - return ALIGN_DOWN(smm_region_start(), 1*MiB); -} - -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The stage cache lives at the end of TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() + northbridge_get_tseg_size() - - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE); -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - top_of_ram = (uintptr_t)cbmem_top(); - /* Cache 8MiB below the top of ram. On sandybridge systems the top of - * ram under 4GiB is the start of the TSEG region. It is required to - * be 8MiB aligned. Set this area as cacheable so it can be used later - * for ramstage before setting up the entire RAM as cacheable. */ - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - - /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems - * is where the TSEG region resides. However, it is not restricted - * to SMM mode until SMM has been relocated. By setting the region - * to cacheable it provides faster access when relocating the SMM - * handler as well as using the TSEG region for other purposes. */ - postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ -} diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 3118b0980e..b7fd2fe7ae 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -19,16 +19,16 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c -romstage-y += ram_calc.c +romstage-y += memmap.c romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c ramstage-y += acpi.c -ramstage-y += ram_calc.c +ramstage-y += memmap.c ramstage-y += gma.c ramstage-y += northbridge.c -postcar-y += ram_calc.c +postcar-y += memmap.c endif diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c new file mode 100644 index 0000000000..dda838760d --- /dev/null +++ b/src/northbridge/intel/x4x/memmap.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +u32 decode_igd_memory_size(const u32 gms) +{ + static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, + 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + + if (gms >= ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +} + +/** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ +u32 decode_igd_gtt_size(const u32 gsm) +{ + static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; + + if (gsm >= ARRAY_SIZE(ggc2gtt)) + die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); + + return ggc2gtt[gsm] << 10; +} + +/** Decodes used TSEG size to bytes. */ +u32 decode_tseg_size(const u32 esmramc) +{ + if (!(esmramc & 1)) + return 0; + + switch ((esmramc >> 1) & 3) { + case 0: + return 1 << 20; + case 1: + return 2 << 20; + case 2: + return 8 << 20; + case 3: + default: + die("Bad TSEG setting.\n"); + } +} + +u8 decode_pciebar(u32 *const base, u32 *const len) +{ + *base = 0; + *len = 0; + const pci_devfn_t dev = PCI_DEV(0, 0, 0); + u32 pciexbar = 0; + u32 pciexbar_reg; + u32 reg32; + int max_buses; + const struct { + u16 num_buses; + u32 addr_mask; + } busmask[] = { + {256, 0xf0000000}, + {128, 0xf8000000}, + {64, 0xfc000000}, + {0, 0}, + }; + + pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); + + if (!(pciexbar_reg & 1)) { + printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); + return 0; + } + + reg32 = (pciexbar_reg >> 1) & 3; + pciexbar = pciexbar_reg & busmask[reg32].addr_mask; + max_buses = busmask[reg32].num_buses; + + if (!pciexbar) { + printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); + return 0; + } + + *base = pciexbar; + *len = max_buses << 20; + return 1; +} + +u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); + return decode_tseg_size(esmramc); +} + +u32 northbridge_get_tseg_base(void) +{ + return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); +} + + +/* Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB alignment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ +void *cbmem_top(void) +{ + uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); + return (void *) top_of_ram; +} + +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of the TSEG region. + * The top of RAM is defined to be the TSEG base address. + */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, 0)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache 8 MiB region below the top of ram and 2 MiB above top of + * ram to cover both cbmem as the TSEG region. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, + MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), + northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); + + run_postcar_phase(&pcf); + + /* We do not return here. */ +} diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c deleted file mode 100644 index dda838760d..0000000000 --- a/src/northbridge/intel/x4x/ram_calc.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ -u32 decode_igd_memory_size(const u32 gms) -{ - static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, - 32, 48, 64, 128, 256, 96, 160, 224, 352 }; - - if (gms >= ARRAY_SIZE(ggc2uma)) - die("Bad Graphics Mode Select (GMS) setting.\n"); - - return ggc2uma[gms] << 10; -} - -/** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ -u32 decode_igd_gtt_size(const u32 gsm) -{ - static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; - - if (gsm >= ARRAY_SIZE(ggc2gtt)) - die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); - - return ggc2gtt[gsm] << 10; -} - -/** Decodes used TSEG size to bytes. */ -u32 decode_tseg_size(const u32 esmramc) -{ - if (!(esmramc & 1)) - return 0; - - switch ((esmramc >> 1) & 3) { - case 0: - return 1 << 20; - case 1: - return 2 << 20; - case 2: - return 8 << 20; - case 3: - default: - die("Bad TSEG setting.\n"); - } -} - -u8 decode_pciebar(u32 *const base, u32 *const len) -{ - *base = 0; - *len = 0; - const pci_devfn_t dev = PCI_DEV(0, 0, 0); - u32 pciexbar = 0; - u32 pciexbar_reg; - u32 reg32; - int max_buses; - const struct { - u16 num_buses; - u32 addr_mask; - } busmask[] = { - {256, 0xf0000000}, - {128, 0xf8000000}, - {64, 0xfc000000}, - {0, 0}, - }; - - pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); - - if (!(pciexbar_reg & 1)) { - printk(BIOS_WARNING, "WARNING: MMCONF not set\n"); - return 0; - } - - reg32 = (pciexbar_reg >> 1) & 3; - pciexbar = pciexbar_reg & busmask[reg32].addr_mask; - max_buses = busmask[reg32].num_buses; - - if (!pciexbar) { - printk(BIOS_WARNING, "WARNING: pciexbar invalid\n"); - return 0; - } - - *base = pciexbar; - *len = max_buses << 20; - return 1; -} - -u32 northbridge_get_tseg_size(void) -{ - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); - return decode_tseg_size(esmramc); -} - -u32 northbridge_get_tseg_base(void) -{ - return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG); -} - - -/* Depending of UMA and TSEG configuration, TSEG might start at any - * 1 MiB alignment. As this may cause very greedy MTRR setup, push - * CBMEM top downwards to 4 MiB boundary. - */ -void *cbmem_top(void) -{ - uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; -} - -void stage_cache_external_region(void **base, size_t *size) -{ - /* The stage cache lives at the end of the TSEG region. - * The top of RAM is defined to be the TSEG base address. - */ - *size = CONFIG_SMM_RESERVED_SIZE; - *base = (void *)((uintptr_t)northbridge_get_tseg_base() - + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); -} - -/* platform_enter_postcar() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use, - * and continues execution in postcar stage. */ -void platform_enter_postcar(void) -{ - struct postcar_frame pcf; - uintptr_t top_of_ram; - - if (postcar_frame_init(&pcf, 0)) - die("Unable to initialize postcar frame.\n"); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Cache 8 MiB region below the top of ram and 2 MiB above top of - * ram to cover both cbmem as the TSEG region. - */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, - MTRR_TYPE_WRBACK); - postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(), - northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); - - run_postcar_phase(&pcf); - - /* We do not return here. */ -} -- cgit v1.2.3