From 79542fa36f919647137737ce2cf2e30042e4fe53 Mon Sep 17 00:00:00 2001
From: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Date: Wed, 10 Mar 2021 03:50:57 -0800
Subject: soc/amd/cezanne: Port ACPI p-state and c-state entries from picasso

Add generate_cpu_entries to device operations. Add support to
generate cpu p-state and c-state SSDT entries.

BUG=b:184151560
TEST=Dump and verify SSDT entry for CPU p-states and c-states.

Change-Id: I77d8078b94fb661dc045b4184955c8cbec373d12
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/cezanne/chip.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/amd/cezanne/chip.c')

diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index c2d7af7f61..8625bd75f1 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -4,6 +4,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
+#include <soc/cpu.h>
 #include <soc/data_fabric.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
@@ -19,6 +20,7 @@ struct device_operations cpu_bus_ops = {
 	.read_resources	= noop_read_resources,
 	.set_resources	= noop_set_resources,
 	.init		= mp_cpu_bus_init,
+	.acpi_fill_ssdt	= generate_cpu_entries,
 };
 
 static const char *soc_acpi_name(const struct device *dev)
-- 
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