From a6529e789f5c460c1b378b3194e795ceb32a5171 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 9 Feb 2021 14:38:36 -0700 Subject: soc/amd/cezanne: Add PCI IRQ Router definitions These definitions were identical to picasso. The only thing I changed was that I renamed Misc1 and Misc2 to HPET_L and HPET_H. This change still doesn't write the PCI_IRQ register for all the PCI devices. We need to refactor the picasso pci_gpp code first. TEST=Boot majolica and see FCH IRQs being programmed. Signed-off-by: Raul E Rangel Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451 Reviewed-by: Mathew King Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h (limited to 'src/soc/amd/cezanne/include') diff --git a/src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h b/src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h new file mode 100644 index 0000000000..f1a5722fba --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_AMD_PCI_INT_DEFS_H +#define AMD_CEZANNE_AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + */ + +#define PIRQ_NC 0x1f /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_HPET_L 0x0a /* HPET TMR{0..2}_CONF_CAP_H[0:7] */ +#define PIRQ_HPET_H 0x0b /* HPET TMR{0..2}_CONF_CAP_H[15:8] */ +#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS */ +#define PIRQ_ASF 0x12 /* ASF */ +/* 0x13-0x15 reserved */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_SD 0x17 /* SD */ +/* 0x18-0x19 reserved */ +#define PIRQ_SDIO 0x1a /* SDIO */ +/* 0x1b-0x1f reserved */ +#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ +#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ +#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ +#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ +/* 0x24-0x40 reserved */ +#define PIRQ_SATA 0x41 /* SATA */ +/* 0x42 reserved */ +#define PIRQ_EMMC 0x43 /* eMMC */ +/* 0x44-0x4f reserved */ +#define PIRQ_GPP0 0x50 /* GPPInt0 */ +#define PIRQ_GPP1 0x51 /* GPPInt1 */ +#define PIRQ_GPP2 0x52 /* GPPInt2 */ +#define PIRQ_GPP3 0x53 /* GPPInt3 */ +/* 0x54-0x61 reserved */ +#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +/* 0x63-0x6f reserved */ +#define PIRQ_I2C0 0x70 /* I2C0 */ +#define PIRQ_I2C1 0x71 /* I2C1 */ +#define PIRQ_I2C2 0x72 /* I2C2 */ +#define PIRQ_I2C3 0x73 /* I2C3 */ +#define PIRQ_UART0 0x74 /* UART0 */ +#define PIRQ_UART1 0x75 /* UART1 */ +#define PIRQ_I2C4 0x76 /* I2C4 */ +#define PIRQ_I2C5 0x77 /* I2C5 */ +/* 0x78-0x7f reserved */ + +#endif /* AMD_CEZANNE_AMD_PCI_INT_DEFS_H */ -- cgit v1.2.3