From e512bce18967d52675653351b7154dc1ab75341d Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Wed, 21 Aug 2019 09:19:13 -0700 Subject: soc/amd/common/block: Create new SPI code Create a new SPI code that overrides flash operations and uses the SPI controller within the FCH to its fullest. Reference: Family 15h models 70h-7Fh BKDG revision 3.06 (public) BUG=b:136595978 TEST=Build and boot grunt using this code, with debug enabled. Check output. Change-Id: Id293fb9b2da84c4206c7a1341b64e83fc0b8d71d Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/c/coreboot/+/35018 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- .../amd/common/block/include/amdblocks/fch_spi.h | 87 ++++++++++++++++++++++ src/soc/amd/common/block/include/amdblocks/lpc.h | 8 ++ 2 files changed, 95 insertions(+) create mode 100644 src/soc/amd/common/block/include/amdblocks/fch_spi.h (limited to 'src/soc/amd/common/block/include') diff --git a/src/soc/amd/common/block/include/amdblocks/fch_spi.h b/src/soc/amd/common/block/include/amdblocks/fch_spi.h new file mode 100644 index 0000000000..24cfbfc74a --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/fch_spi.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Silverback Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _FCH_SPI_H_ +#define _FCH_SPI_H_ + +#include +#include + +#define GRANULARITY_TEST_4k 0x0000f000 /* bits 15-12 */ +#define WORD_TO_DWORD_UPPER(x) ((x << 16) & 0xffff0000) +#define SPI_PAGE_WRITE 0x02 +#define SPI_WRITE_ENABLE 0x06 +#define IDCODE_CONT_LEN 0 +#define IDCODE_PART_LEN 5 +#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) + +/* SPI MMIO registers */ +#define SPI_CNTRL0 0x00 +#define SPI_ACCESS_MAC_ROM_EN BIT(22) +#define SPI_RESTRICTED_CMD1 0x04 +#define SPI_RESTRICTED_CMD2 0x08 +#define SPI_CNTRL1 0x0c +#define SPI_CMD_CODE 0x45 +#define SPI_CMD_TRIGGER 0x47 + +/* Special SST write commands */ +#define CMD_SST_BP 0x02 /* Byte Program */ +#define CMD_SST_AAI_WP 0xad /* Auto Address Increment Word Program */ + +#define SST_256 0x004b /* Only SST that programs 256 bytes at once */ + +enum non_standard_spi { + NON_STANDARD_SPI_NONE = 0, + NON_STANDARD_SPI_SST, +}; + +struct spi_flash_table { + const u8 shift; + const u8 idcode; + int (*probe)(const struct spi_slave *spi, u8 *idcode, + struct spi_flash *flash); +}; + +struct spi_data { + const char *name; + u32 size; + u32 sector_size; + u32 page_size; + u8 status_cmd; + u8 erase_cmd; + u8 write_cmd; + u8 write_enable_cmd; + u8 read_cmd; + u8 read_cmd_len; + enum non_standard_spi non_standard; +}; + +void fch_spi_init(void); +void fch_spi_flash_ops_init(struct spi_flash *flash); +int fch_spi_flash_cmd(const void *dout, size_t bytes_out, void *din, size_t bytes_in); +int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, size_t data_len); +int fch_spi_wait_cmd_ready(unsigned long timeout); +int non_standard_sst_byte_write(u32 offset, const void *buf); +int non_standard_sst_write_aai(u32 offset, size_t len, const void *buf, size_t start); +const struct spi_flash_table *get_spi_flash_table(int *table_size); +const struct spi_data *get_ctrl_spi_data(void); + +static inline int fch_spi_enable_write(void) +{ + u8 cmd_enable = SPI_WRITE_ENABLE; + return fch_spi_flash_cmd(&cmd_enable, 1, NULL, 0); +} + +#endif /* _FCH_SPI_H_ */ diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index f956ba3aa9..11880eb3e6 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -90,6 +90,14 @@ #define DECODE_IO_PORT_ENABLE0_H BIT(0) #define LPC_MEM_PORT1 0x4c +#define ROM_PROTECT_RANGE0 0x50 +#define ROM_BASE_MASK 0xfffff000 /* bits 31-12 */ +#define ROM_RANGE_WP BIT(10) +#define ROM_RANGE_RP BIT(9) +#define RANGE_UNIT BIT(8) +#define RANGE_ADDR_MASK 0x000000ff /* Range defined by bits 7-0 */ +#define ROM_PROTECT_RANGE_REG(n) (ROM_PROTECT_RANGE0 + (4 * n)) +#define MAX_ROM_PROTECT_RANGES 4 #define LPC_MEM_PORT0 0x60 /* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. -- cgit v1.2.3