From 34fc29ae96d2ae6e0d021c84fc3ff8d56ec38898 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 11 Feb 2021 02:43:07 +0100 Subject: soc/amd: add and use fch_enable_hpet_decode On Picasso we missed setting this bit in coreboot and since the default after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge and Cezanne have the HPET decode enable bit in the same position in the same register. In the ACPI table entry written by southbridge_write_acpi_tables the HPET entry gets added, so we should make sure that we enable the decode. TEST=HPET still works on Mandolin. Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512 Reviewed-by: Raul Rangel Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/smbus/sm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/common/block/smbus/sm.c') diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 0b219e006d..b1b3db6192 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -13,6 +13,7 @@ static void sm_init(struct device *dev) { fch_enable_ioapic_decode(); setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); + fch_configure_hpet(); } static u32 get_sm_mmio(struct device *dev) -- cgit v1.2.3