From befec1e92ef3dca5e7e7cf8e5c8c465e22f68ea2 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 6 Nov 2020 00:26:03 +0100 Subject: soc/amd/common: add Kconfig help text to pre-family-17h-only blocks The cpu/car code only applies to pre-family-17h CPUs that still use cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor code blob binaryPI interface. Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274 Reviewed-by: Marshall Dawson Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/cpu/Kconfig | 3 +++ src/soc/amd/common/block/pi/Kconfig | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/common') diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 5941599df0..f6756e18f8 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -8,3 +8,6 @@ config SOC_AMD_COMMON_BLOCK_CAR it may not be appropriate for a romstage implementation without additional consideration. If this option is not used, the SOC must implement these functions separately. + This is only used for AMD CPU before family 17h. From family 17h on + the RAM is already initialized by the PSP before the x86 cores are + released from reset. diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig index f0917bb767..cf8c79ae50 100644 --- a/src/soc/amd/common/block/pi/Kconfig +++ b/src/soc/amd/common/block/pi/Kconfig @@ -3,7 +3,8 @@ config SOC_AMD_COMMON_BLOCK_PI select HAVE_DEBUG_RAM_SETUP default n help - This option builds functions that interface AMD's AGESA. + This option builds functions that interface AMD's AGESA reference + code packaged in the binaryPI form. if SOC_AMD_COMMON_BLOCK_PI -- cgit v1.2.3