From 39a4ac1502b658d4ef6b57c50a0e386eff91364a Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 20 Jun 2019 16:28:33 -0600 Subject: soc/amd/picasso: Update southbridge Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR * Add option to determine the intended MUX settion for LPC vs. eMMC * Remove the LEGACY_FREE option Signed-off-by: Marshall Dawson Change-Id: I69dfc4a875006639aa330385680d150331840e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/soc/amd/picasso/Kconfig') diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4580915a79..9447fd7e77 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -178,12 +178,6 @@ config AHCI_ROM_ID endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 -config PICASSO_LEGACY_FREE - bool "System is legacy free" - help - Select y if there is no keyboard controller in the system. - This sets a variable in ACPI. - config SERIRQ_CONTINUOUS_MODE bool default n @@ -251,6 +245,12 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ int default 133 +config PICASSO_LPC_IOMUX + bool + help + Picasso's LPC bus signals are MUXed with some of the EMMC signals. + Select this option if LPC signals are required. + config MAINBOARD_POWER_RESTORE def_bool n help -- cgit v1.2.3