From 80d0b01b38049775750c14cb0e0d978afb780ca1 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Wed, 19 Jun 2019 12:29:23 -0600 Subject: soc/amd/picasso: Update TSC and monotonic timer Picasso's TimeStamp Counter is a new design and different than Stoney Ridge. Although advertised as invariant, the ST TSC did not become so until midway through POST making it an unreliable source for measuring time. This is not the case for Picasso. Remove the Stoney Ridge monotonic timer code and rely on the TSC. Modify the calculation used in Family 15h of finding the number of boost states first, and get the frequency directly out of the Pstate0 register. Signed-off-by: Marshall Dawson Change-Id: I909743483309279eb8c3bf68852d6082381f0dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/soc/amd/picasso/Kconfig | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src/soc/amd/picasso/Kconfig') diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 26b2ec4302..b3ee50c97d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,14 +29,15 @@ config CPU_SPECIFIC_OPTIONS select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI select ACPI_AMD_HARDWARE_SLEEP_VALUES - select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB - select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS select SPI_FLASH if HAVE_ACPI_RESUME + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select TSC_SYNC_LFENCE + select UDELAY_TSC select COLLECT_TIMESTAMPS select SOC_AMD_PI select SOC_AMD_COMMON @@ -66,10 +67,6 @@ config VBOOT select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH -config UDELAY_LAPIC_FIXED_FSB - int - default 200 - config HAVE_BOOTBLOCK bool default n -- cgit v1.2.3