From 39bd46f4a4f3c1cc76f1007f82050c943fd09bb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 18 Jun 2020 19:18:21 +0300 Subject: soc/amd/common: Drop ACPIMMIO GPIO bank separation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL takes advantage of the property. Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522 Reviewed-by: Raul Rangel Reviewed-by: Furquan Shaikh Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/i2c.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/soc/amd/picasso/include') diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 58c27a424d..34c19aaf29 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -17,11 +17,6 @@ struct soc_amd_i2c_save { #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19 -#define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) -#define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) -#define GPIO_SCL_HIGH 0 -#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE - #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx -- cgit v1.2.3