From 39c64b0bdd04a84bf206be5a94ceb1d685e9e1a8 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 4 Sep 2020 12:07:27 -0600 Subject: soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass the info to FSP to keep it in sync with coreboot. Do the same for the northbridge's IOAPIC base address. Use the new values where needed, and reserve the resources consumed by the GNB IOAPIC. BUG=b:167421913, b:166519072 TEST=Boot Morphius and verify settings BRANCH=Zork Signed-off-by: Marshall Dawson Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115 Reviewed-by: Furquan Shaikh Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/iomap.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/amd/picasso/include') diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 825683653a..890b1c3647 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -5,6 +5,7 @@ /* MMIO Ranges */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ +#define GNB_IO_APIC_ADDR 0xfec01000 #define SPI_BASE_ADDRESS 0xfec10000 #if CONFIG(HPET_ADDRESS_OVERRIDE) -- cgit v1.2.3