From ab83b43b34d729ad260d8f68b725ed025eaafb5e Mon Sep 17 00:00:00 2001 From: Matt Papageorge Date: Fri, 26 Jun 2020 08:47:00 -0500 Subject: soc/amd/picasso/sb: Gate FCH AL2AHB clocks Gate the A-Link to AHB Bridge clocks to save power. These are internal clocks and are unneeded for Raven/Picasso. This was previously performed within the AGESA FSP but this change relocates it into coreboot. BUG=b:154144239 TEST=Check AL2AHB clock gate bits at the end of POST before and after change with HDT. Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9 Signed-off-by: Matt Papageorge Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons Reviewed-by: Furquan Shaikh --- src/soc/amd/picasso/include/soc/iomap.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/amd/picasso/include') diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index cb845c44d3..6b9ad2a005 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -12,7 +12,12 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 +/* FCH AL2AHB Registers */ #define ALINK_AHB_ADDRESS 0xfedc0000 +#define AL2AHB_CONTROL_CLK_OFFSET 0x10 +#define AL2AHB_CLK_GATE_EN (1 << 1) +#define AL2AHB_CONTROL_HCLK_OFFSET 0x30 +#define AL2AHB_HCLK_GATE_EN (1 << 1) /* Reserved 0xfecd1000-0xfedc3fff */ -- cgit v1.2.3