From d82c7d24ffc64e7caeaff6ccd7c79d3946142afc Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 9 May 2020 17:18:48 -0700 Subject: soc/amd/common/block/lpc: Split lpc_set_spibase() into two functions This change splits lpc_set_spibase() into two separate functions: lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI controller (if supported by platforms) lpc_enable_spi_rom() - Enables SPI ROM This split is done to allow setting of MMIO base independent of ROM enable bits. On platforms like Picasso, eSPI base is determined by the same register and hence eSPI can set the BAR without having to touch the enable bits. Signed-off-by: Furquan Shaikh Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Aaron Durbin Reviewed-by: Felix Held --- src/soc/amd/picasso/southbridge.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/picasso/southbridge.c') diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 73ab03b643..6308953fc6 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -207,7 +207,9 @@ static uintptr_t sb_init_spi_base(void) if (base) return base; - lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + lpc_set_spibase(SPI_BASE_ADDRESS); + lpc_enable_spi_rom(SPI_ROM_ENABLE); + return SPI_BASE_ADDRESS; } -- cgit v1.2.3