From 152a5e19169564e751a06126a45c71f5fbe68ab2 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 16 Jul 2019 09:37:16 -0600 Subject: soc/amd: Move SPI base alignment define into common The decision to leave the alignment in stoneyridge was driven because of a spec difference with picasso. AMD has checked the design materials and has confirmed there was no change. TEST=Build Grunt successfully BUG=b:130343127 Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/picasso/include/soc/southbridge.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 565ab3084d..6fc37f009a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -225,9 +225,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* SPI Controller (base address in D14F3xA0) */ -#define SPI_BASE_ALIGNMENT BIT(6) - #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -- cgit v1.2.3