From 21c46c089ca7116fc52f756103cb2d2193b738e1 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 5 Mar 2021 00:13:16 +0100 Subject: soc/amd/picasso: move APOB NV cache to common code Also rename mrc_cache to apob_cache. BUG=b:181766974 Signed-off-by: Felix Held Change-Id: I4877b05443452c7409006c1656e9d574e93150a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51267 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/Makefile.inc | 1 - src/soc/amd/picasso/include/soc/mrc_cache.h | 9 -- src/soc/amd/picasso/mrc_cache.c | 174 ---------------------------- src/soc/amd/picasso/romstage.c | 6 +- 5 files changed, 4 insertions(+), 187 deletions(-) delete mode 100644 src/soc/amd/picasso/include/soc/mrc_cache.h delete mode 100644 src/soc/amd/picasso/mrc_cache.c (limited to 'src/soc/amd/picasso') diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dba95b62e5..ea9ee5bb3f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC + select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_GRAPHICS diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index c8cc458da0..5ef47af9ca 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -24,7 +24,6 @@ romstage-y += romstage.c romstage-y += gpio.c romstage-y += reset.c romstage-y += uart.c -romstage-y += mrc_cache.c verstage-y += i2c.c verstage_x86-y += gpio.c diff --git a/src/soc/amd/picasso/include/soc/mrc_cache.h b/src/soc/amd/picasso/include/soc/mrc_cache.h deleted file mode 100644 index c7fcedbdd9..0000000000 --- a/src/soc/amd/picasso/include/soc/mrc_cache.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef AMD_PICASSO_MRC_CACHE_H -#define AMD_PICASSO_MRC_CACHE_H - -void *soc_fill_mrc_cache(void); -void soc_update_mrc_cache(void); - -#endif /* AMD_PICASSO_MRC_CACHE_H */ diff --git a/src/soc/amd/picasso/mrc_cache.c b/src/soc/amd/picasso/mrc_cache.c deleted file mode 100644 index 24d86e01ac..0000000000 --- a/src/soc/amd/picasso/mrc_cache.c +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DEFAULT_MRC_CACHE "RW_MRC_CACHE" -/* PSP requires this value to be 64KiB */ -#define DEFAULT_MRC_CACHE_SIZE 0x10000 - -#if !CONFIG_PSP_APOB_DRAM_ADDRESS -#error Incorrect APOB configuration setting(s) -#endif - -#define APOB_SIGNATURE 0x424F5041 /* 'APOB' */ - -/* APOB_BASE_HEADER from AGESA */ -struct apob_base_header { - uint32_t signature; /* APOB signature */ - uint32_t version; /* Version */ - uint32_t size; /* APOB Size */ - uint32_t offset_of_first_entry; /* APOB Header Size */ -}; - -static bool apob_header_valid(const struct apob_base_header *apob_header_ptr, const char *where) -{ - if (apob_header_ptr->signature != APOB_SIGNATURE) { - printk(BIOS_WARNING, "Invalid %s APOB signature %x\n", - where, apob_header_ptr->signature); - return false; - } - - if (apob_header_ptr->size == 0 || apob_header_ptr->size > DEFAULT_MRC_CACHE_SIZE) { - printk(BIOS_WARNING, "%s APOB data is too large %x > %x\n", - where, apob_header_ptr->size, DEFAULT_MRC_CACHE_SIZE); - return false; - } - - return true; -} - -static void *get_apob_dram_address(void) -{ - /* - * TODO: Find the APOB destination by parsing the PSP's tables - * (once vboot is implemented). - */ - void *apob_src_ram = (void *)(uintptr_t)CONFIG_PSP_APOB_DRAM_ADDRESS; - - if (apob_header_valid(apob_src_ram, "RAM") == false) - return NULL; - - return apob_src_ram; -} - -static int get_nv_region(struct region *r) -{ - if (fmap_locate_area(DEFAULT_MRC_CACHE, r) < 0) { - printk(BIOS_ERR, "Error: No APOB NV region is found in flash\n"); - return -1; - } - - return 0; -} - -static void *get_apob_from_nv_region(struct region *region) -{ - struct region_device read_rdev; - struct apob_base_header apob_header; - - if (boot_device_ro_subregion(region, &read_rdev) < 0) { - printk(BIOS_ERR, "Failed boot_device_ro_subregion\n"); - return NULL; - } - - if (rdev_readat(&read_rdev, &apob_header, 0, sizeof(apob_header)) < 0) { - printk(BIOS_ERR, "Couldn't read APOB header!\n"); - return NULL; - } - - if (apob_header_valid(&apob_header, "ROM") == false) { - printk(BIOS_ERR, "No APOB NV data!\n"); - return NULL; - } - - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - return rdev_mmap_full(&read_rdev); -} - -/* Save APOB buffer to flash */ -void soc_update_mrc_cache(void) -{ - struct apob_base_header *apob_rom; - struct region_device write_rdev; - struct region region; - bool update_needed = false; - const struct apob_base_header *apob_src_ram; - - /* Nothing to update in case of S3 resume. */ - if (acpi_is_wakeup_s3()) - return; - - apob_src_ram = get_apob_dram_address(); - if (apob_src_ram == NULL) - return; - - if (get_nv_region(®ion) != 0) - return; - - apob_rom = get_apob_from_nv_region(®ion); - if (apob_rom == NULL) { - update_needed = true; - } else if (memcmp(apob_src_ram, apob_rom, apob_src_ram->size)) { - printk(BIOS_INFO, "APOB RAM copy differs from flash\n"); - update_needed = true; - } else - printk(BIOS_DEBUG, "APOB valid copy is already in flash\n"); - - if (!update_needed) - return; - - printk(BIOS_SPEW, "Copy APOB from RAM 0x%p/0x%x to flash 0x%zx/0x%zx\n", - apob_src_ram, apob_src_ram->size, - region_offset(®ion), region_sz(®ion)); - - if (boot_device_rw_subregion(®ion, &write_rdev) < 0) { - printk(BIOS_ERR, "Failed boot_device_rw_subregion\n"); - return; - } - - /* write data to flash region */ - if (rdev_eraseat(&write_rdev, 0, DEFAULT_MRC_CACHE_SIZE) < 0) { - printk(BIOS_ERR, "Error: APOB flash region erase failed\n"); - return; - } - - if (rdev_writeat(&write_rdev, apob_src_ram, 0, apob_src_ram->size) < 0) { - printk(BIOS_ERR, "Error: APOB flash region update failed\n"); - return; - } - - printk(BIOS_INFO, "Updated APOB in flash\n"); -} - -static void *get_apob_nv_address(void) -{ - struct region region; - - if (get_nv_region(®ion) != 0) - return NULL; - - return get_apob_from_nv_region(®ion); -} - -void *soc_fill_mrc_cache(void) -{ - /* If this is non-S3 boot, then use the APOB data placed by PSP in DRAM. */ - if (!acpi_is_wakeup_s3()) - return get_apob_dram_address(); - - /* - * In case of S3 resume, PSP does not copy APOB data to DRAM. Thus, coreboot needs to - * provide the APOB NV data from RW_MRC_CACHE on SPI flash so that FSP can use it - * without having to traverse the BIOS directory table. - */ - return get_apob_nv_address(); -} diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index c085a5355f..ecee4d3fe9 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -14,7 +15,6 @@ #include #include #include -#include #include #include #include "chip.h" @@ -92,7 +92,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *mcfg = &mupd->FspmConfig; const struct soc_amd_picasso_config *config = config_of_soc(); - mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_mrc_cache(); + mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE; @@ -153,7 +153,7 @@ asmlinkage void car_stage_entry(void) post_code(0x43); fsp_memory_init(acpi_is_wakeup_s3()); - soc_update_mrc_cache(); + soc_update_apob_cache(); memmap_stash_early_dram_usage(); -- cgit v1.2.3