From 24079323d4d83db4ce0ff0646309bd644b53aa76 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 23 Jan 2018 10:53:05 -0700 Subject: soc/amd/stoneyridge: provide alternate monotonic timer The TSC has been observed to be ticking at a non-constant rate in early boot. The root cause is still not known, but this misbehavior necessitates an alternative monotonic timer source. Use the perf TSC which ticks at 100 MHz. This also means the timestamp table is not accurate as well. Root cause of TSC rate instability needs to be resolved in order to fix that. BUG=b:72170796 Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/23397 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest --- src/soc/amd/stoneyridge/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'src/soc/amd/stoneyridge/Kconfig') diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 51573fe34f..4f07db8a39 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select UDELAY_TSC select HAVE_MONOTONIC_TIMER - select TSC_MONOTONIC_TIMER select TSC_CONSTANT_RATE select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE -- cgit v1.2.3