From 51e4c1a76cafa0ddd429ffa78d0e6fdee179f731 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 24 Jan 2018 17:42:51 -0700 Subject: soc/amd/stoneyridge: remove dependence on TSC The TSC rate is empirically swinging during early boot. That leaves timestamps and udelay()s to not be correct. To rectify this stop using TSC for all of these time sources. Instead use the performance TSC which is at a fixed 100MHz clock. That provides stable time sources and legit timestamps. BUG=b:72378235,b:72170796 Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/23424 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/amd/stoneyridge/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/amd/stoneyridge/Kconfig') diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index fbeabb71cd..148ca3ff04 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -32,14 +32,14 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ACPI_AMD_HARDWARE_SLEEP_VALUES + select COLLECT_TIMESTAMPS_NO_TSC select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB + select GENERIC_UDELAY select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET - select UDELAY_TSC select HAVE_MONOTONIC_TIMER - select TSC_CONSTANT_RATE select SPI_FLASH if HAVE_ACPI_RESUME select TSC_SYNC_LFENCE select COLLECT_TIMESTAMPS -- cgit v1.2.3