From 18b477ea4108335eb6d5a4b6f39578cbe5525ac1 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 21 Sep 2017 12:27:12 -0600 Subject: soc/amd/stoneyridge: Add postcar stage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Insert a postcar stage for Stoney Ridge and move romstage's CAR teardown there. The AMD cache-as-ram teardown procedure currently uses a wbinvd instruction to send CAR contents to DRAM backing. This allows preserving stack contents and CAR globals after the teardown happens, but likely results in memory corruption during S3 resume. Due to the current base of the DCACHE region, reverting to an invd instruction will break the detection mechanism for CAR migrated variables. Using postcar avoids this problem. The current behavior of AGESA is to set up all cores' MTRRs during the AmdInitPost() entry point. This implementation takes control back and causes postcar's _start to clear all settings and set attributes only for the BIOS flash device, TSEG, and enough space below cbmem_top to load and run ramstage. BUG=b:64768556 Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/20966 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Aaron Durbin --- src/soc/amd/stoneyridge/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/amd/stoneyridge/Makefile.inc') diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 5d8973616a..0fd318bfa6 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -63,6 +63,9 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c +postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-y += ramtop.c + ramstage-y += chip.c ramstage-y += cpu.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -- cgit v1.2.3