From 1587dc8a2b4ddfe110cd0239c6506a320cccac96 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 15 May 2017 18:55:11 -0600 Subject: soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/chip.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/soc/amd/stoneyridge/chip.h') diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 9dd4997931..f913b055a2 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ struct soc_amd_stoneyridge_config { + u8 spdAddrLookup[1][1][2]; u32 ide0_enable : 1; u32 sata0_enable : 1; u32 boot_switch_sata_ide : 1; @@ -30,4 +31,6 @@ struct soc_amd_stoneyridge_config typedef struct soc_amd_stoneyridge_config config_t; +extern struct device_operations pci_domain_ops; + #endif /* STONEYRIDGE_CHIP_H */ -- cgit v1.2.3