From 244848462def7075e0c812a2f71c408668cacfe4 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Thu, 4 May 2017 21:17:45 -0600 Subject: soc: Add AMD Stoney Ridge southbridge code Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/chip.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 src/soc/amd/stoneyridge/chip.h (limited to 'src/soc/amd/stoneyridge/chip.h') diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h new file mode 100644 index 0000000000..9dd4997931 --- /dev/null +++ b/src/soc/amd/stoneyridge/chip.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STONEYRIDGE_CHIP_H +#define STONEYRIDGE_CHIP_H + +#include + +struct soc_amd_stoneyridge_config +{ + u32 ide0_enable : 1; + u32 sata0_enable : 1; + u32 boot_switch_sata_ide : 1; + u32 hda_viddid; + u8 gpp_configuration; + u8 sd_mode; +}; + +typedef struct soc_amd_stoneyridge_config config_t; + +#endif /* STONEYRIDGE_CHIP_H */ -- cgit v1.2.3