From 2e49cf129ac0f3326989cd1202904a3f02d1d467 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Fri, 3 Aug 2018 17:05:22 -0600 Subject: amd/stoneyridge: Add warm reset detection Extend the existing reset handling features in Stoney Ridge to plan for, and recognize, warm resets. The ColdRstDet bit is always zero on a cold reset, and is intended as a mechanism for the BIOS to determine the type of a reset that occurred. Set ColdRstDet=1 after all cores have been initialized, so that any subsequent reset may be identified as warm/cold. A later patch will check the value during mp_init. Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/27924 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/cpu.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/amd/stoneyridge/cpu.c') diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 7fff1203aa..52b1c9cbb1 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -113,6 +113,8 @@ void stoney_init_cpus(struct device *dev) /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + set_warm_reset_flag(); } static void model_15_init(struct device *dev) -- cgit v1.2.3