From 4ee83b2f9435fe08cb73ba818b567597cafd973d Mon Sep 17 00:00:00 2001
From: Marshall Dawson <marshalldawson3rd@gmail.com>
Date: Fri, 3 May 2019 11:44:22 -0600
Subject: soc/amd/stoneyridge: Relocate MMIO access of ACPI registers

The AcpiMmio block allowing direct access to the ACPI registers
has remained consistent across AMD models.  Move the support from
soc//stoneyridge to soc//common.

BUG=b:131682806

Change-Id: I0e017a71f8efb4b614986cb327de398644599853
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/amd/stoneyridge/southbridge.c | 81 +----------------------------------
 1 file changed, 2 insertions(+), 79 deletions(-)

(limited to 'src/soc/amd/stoneyridge/southbridge.c')

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index cd910319a5..10a23f2737 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -22,12 +22,12 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
-#include <elog.h>
 #include <amdblocks/amd_pci_util.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/reset.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/lpc.h>
+#include <amdblocks/acpi.h>
 #include <soc/southbridge.h>
 #include <soc/smbus.h>
 #include <soc/smi.h>
@@ -522,83 +522,6 @@ static void sb_init_acpi_ports(void)
 				PM_ACPI_TIMER_EN_EN);
 }
 
-static uint16_t reset_pm1_status(void)
-{
-	uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS);
-	acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts);
-	return pm1_sts;
-}
-
-static uint16_t print_pm1_status(uint16_t pm1_sts)
-{
-	static const char *const pm1_sts_bits[16] = {
-		[0] = "TMROF",
-		[4] = "BMSTATUS",
-		[5] = "GBL",
-		[8] = "PWRBTN",
-		[10] = "RTC",
-		[14] = "PCIEXPWAK",
-		[15] = "WAK",
-	};
-
-	if (!pm1_sts)
-		return 0;
-
-	printk(BIOS_DEBUG, "PM1_STS: ");
-	print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits);
-	printk(BIOS_DEBUG, "\n");
-
-	return pm1_sts;
-}
-
-static void sb_log_pm1_status(uint16_t pm1_sts)
-{
-	if (!CONFIG(ELOG))
-		return;
-
-	if (pm1_sts & WAK_STS)
-		elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
-				    acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5);
-
-	if (pm1_sts & PWRBTN_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
-
-	if (pm1_sts & RTC_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
-
-	if (pm1_sts & PCIEXPWAK_STS)
-		elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
-}
-
-static void sb_save_sws(uint16_t pm1_status)
-{
-	struct soc_power_reg *sws;
-	uint32_t reg32;
-	uint16_t reg16;
-
-	sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg));
-	if (sws == NULL)
-		return;
-	sws->pm1_sts = pm1_status;
-	sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN);
-	reg32 = acpi_read32(MMIO_ACPI_GPE0_STS);
-	acpi_write32(MMIO_ACPI_GPE0_STS, reg32);
-	sws->gpe0_sts = reg32;
-	sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN);
-	reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
-	reg16 &= SLP_TYP;
-	sws->wake_from = reg16 >> SLP_TYP_SHIFT;
-}
-
-static void sb_clear_pm1_status(void)
-{
-	uint16_t pm1_sts = reset_pm1_status();
-
-	sb_save_sws(pm1_sts);
-	sb_log_pm1_status(pm1_sts);
-	print_pm1_status(pm1_sts);
-}
-
 static int get_index_bit(uint32_t value, uint16_t limit)
 {
 	uint16_t i;
@@ -651,7 +574,7 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
 void southbridge_init(void *chip_info)
 {
 	sb_init_acpi_ports();
-	sb_clear_pm1_status();
+	acpi_clear_pm1_status();
 }
 
 static void set_sb_final_nvs(void)
-- 
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