From dfeb1c4da9be7ac97bd31f580ff2fff0c4b3256e Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Mon, 7 Aug 2017 19:08:24 -0600 Subject: stoneyridge: Rename hudson to southbridge Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/Makefile.inc | 2 +- src/soc/amd/stoneyridge/acpi.c | 6 +- src/soc/amd/stoneyridge/acpi/fch.asl | 2 +- src/soc/amd/stoneyridge/bootblock/bootblock.c | 4 +- src/soc/amd/stoneyridge/chip.c | 8 +- src/soc/amd/stoneyridge/dimmSpd.c | 2 +- src/soc/amd/stoneyridge/early_setup.c | 43 +++-- src/soc/amd/stoneyridge/enable_usbdebug.c | 2 +- src/soc/amd/stoneyridge/hda.c | 2 +- src/soc/amd/stoneyridge/hudson.c | 126 ------------- src/soc/amd/stoneyridge/include/soc/hudson.h | 209 ---------------------- src/soc/amd/stoneyridge/include/soc/smi.h | 8 +- src/soc/amd/stoneyridge/include/soc/southbridge.h | 207 +++++++++++++++++++++ src/soc/amd/stoneyridge/lpc.c | 20 +-- src/soc/amd/stoneyridge/reset.c | 2 +- src/soc/amd/stoneyridge/romstage.c | 2 +- src/soc/amd/stoneyridge/sata.c | 2 +- src/soc/amd/stoneyridge/sm.c | 14 +- src/soc/amd/stoneyridge/smbus_spd.c | 4 +- src/soc/amd/stoneyridge/smi.c | 2 +- src/soc/amd/stoneyridge/smi_util.c | 6 +- src/soc/amd/stoneyridge/smihandler.c | 7 +- src/soc/amd/stoneyridge/southbridge.c | 126 +++++++++++++ src/soc/amd/stoneyridge/uart.c | 2 +- src/soc/amd/stoneyridge/usb.c | 2 +- 25 files changed, 403 insertions(+), 407 deletions(-) delete mode 100644 src/soc/amd/stoneyridge/hudson.c delete mode 100644 src/soc/amd/stoneyridge/include/soc/hudson.h create mode 100644 src/soc/amd/stoneyridge/include/soc/southbridge.h create mode 100644 src/soc/amd/stoneyridge/southbridge.c (limited to 'src/soc/amd/stoneyridge') diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 30006b3a05..8fa5afbb39 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -66,7 +66,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += fixme.c ramstage-y += gpio.c ramstage-y += hda.c -ramstage-y += hudson.c +ramstage-y += southbridge.c ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += model_15_init.c diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 54af59b59d..9ebe8dea7e 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include @@ -84,7 +84,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->dsdt = (u32) dsdt; fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; - fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ + fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { fadt->smi_cmd = ACPI_SMI_CTL_PORT; @@ -111,7 +111,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->pm2_cnt_blk = 0x0000; fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; fadt->gpe0_blk = ACPI_GPE0_BLK; - fadt->gpe1_blk = 0x0000; /* No gpe1 block in hudson */ + fadt->gpe1_blk = 0x0000; /* No gpe1 block */ fadt->pm1_evt_len = 4; /* 32 bits */ fadt->pm1_cnt_len = 2; /* 16 bits */ diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/fch.asl index 1e0c889866..6a815b33ff 100644 --- a/src/soc/amd/stoneyridge/acpi/fch.asl +++ b/src/soc/amd/stoneyridge/acpi/fch.asl @@ -157,7 +157,7 @@ Method(_INI, 0) { #if IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) /* TODO: It is unstable. */ - #include "acpi/AmdImc.asl" /* Hudson IMC function */ + #include "acpi/AmdImc.asl" ITZE() /* enable IMC Fan Control*/ #endif } /* End Method(_SB._INI) */ diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 473b118d11..3f01603b14 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -47,7 +47,7 @@ void bootblock_soc_early_init(void) post_code(0x90); if (CONFIG_STONEYRIDGE_UART) - configure_hudson_uart(); + configure_stoneyridge_uart(); } void bootblock_soc_init(void) diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 2af466bc8f..3641706483 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include static void cpu_bus_init(device_t dev) @@ -58,17 +58,17 @@ static void enable_dev(device_t dev) else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; else if (dev->path.type == DEVICE_PATH_PCI) - hudson_enable(dev); + sb_enable(dev); } static void soc_init(void *chip_info) { - hudson_init(chip_info); + southbridge_init(chip_info); } static void soc_final(void *chip_info) { - hudson_final(chip_info); + southbridge_final(chip_info); fam15_finalize(chip_info); } diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimmSpd.c index a69b80c69f..ace22bbb4f 100644 --- a/src/soc/amd/stoneyridge/dimmSpd.c +++ b/src/soc/amd/stoneyridge/dimmSpd.c @@ -43,7 +43,7 @@ AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, [info->SocketId][info->MemChannelId][info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *)info->Buffer, 128); + int err = sb_readSpd(spdAddress, (void *)info->Buffer, 128); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index c1a2978c0e..5166a7f5e8 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -21,13 +21,13 @@ #include #include #include -#include +#include #include #include #include #include -void configure_hudson_uart(void) +void configure_stoneyridge_uart(void) { u8 byte; @@ -50,7 +50,7 @@ void configure_hudson_uart(void) + 0x88, 0x01); } -void hudson_pci_port80(void) +void sb_pci_port80(void) { u8 byte; pci_devfn_t dev; @@ -62,7 +62,7 @@ void hudson_pci_port80(void) pci_write_config8(dev, 0x4a, byte); } -void hudson_lpc_port80(void) +void sb_lpc_port80(void) { u8 byte; pci_devfn_t dev; @@ -81,7 +81,7 @@ void hudson_lpc_port80(void) pci_write_config8(dev, 0x4a, byte); } -void hudson_lpc_decode(void) +void sb_lpc_decode(void) { pci_devfn_t dev; u32 tmp = 0; @@ -222,7 +222,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -void hudson_clk_output_48Mhz(void) +void sb_clk_output_48Mhz(void) { u32 ctrl; @@ -237,7 +237,7 @@ void hudson_clk_output_48Mhz(void) write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); } -static uintptr_t hudson_spibase(void) +static uintptr_t sb_spibase(void) { /* Make sure the base address is predictable */ device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); @@ -256,9 +256,9 @@ static uintptr_t hudson_spibase(void) return (uintptr_t)base; } -void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write16((void *)base + SPI100_SPEED_CONFIG, (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | @@ -267,33 +267,32 @@ void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); } -void hudson_disable_4dw_burst(void) +void sb_disable_4dw_burst(void) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write16((void *)base + SPI100_HOST_PREF_CONFIG, read16((void *)base + SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); } -/* Hudson 1-3 only. For Hudson 1, call with fast=1 */ -void hudson_set_readspeed(u16 norm, u16 fast) +void sb_set_readspeed(u16 norm, u16 fast) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) & ~SPI_CNTRL1_SPEED_MASK) | (norm << SPI_NORM_SPEED_SH) | (fast << SPI_FAST_SPEED_SH)); } -void hudson_read_mode(u32 mode) +void sb_read_mode(u32 mode) { - uintptr_t base = hudson_spibase(); + uintptr_t base = sb_spibase(); write32((void *)base + SPI_CNTRL0, (read32((void *)base + SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); } -void hudson_tpm_decode_spi(void) +void sb_tpm_decode_spi(void) { device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */ @@ -308,10 +307,10 @@ void hudson_tpm_decode_spi(void) * Hardware should enable LPC ROM by pin straps. This function does not * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. * - * The HUDSON power-on default is to map 512K ROM space. + * The southbridge power-on default is to map 512K ROM space. * */ -void hudson_enable_rom(void) +void sb_enable_rom(void) { u8 reg8; pci_devfn_t dev; @@ -345,7 +344,7 @@ void hudson_enable_rom(void) void bootblock_fch_early_init(void) { - hudson_enable_rom(); - hudson_lpc_port80(); - hudson_lpc_decode(); + sb_enable_rom(); + sb_lpc_port80(); + sb_lpc_decode(); } diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index 7ed6721a48..efe34e5141 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #define DEBUGPORT_MISC_CONTROL 0x80 diff --git a/src/soc/amd/stoneyridge/hda.c b/src/soc/amd/stoneyridge/hda.c index 2623236974..b41b999925 100644 --- a/src/soc/amd/stoneyridge/hda.c +++ b/src/soc/amd/stoneyridge/hda.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, diff --git a/src/soc/amd/stoneyridge/hudson.c b/src/soc/amd/stoneyridge/hudson.c deleted file mode 100644 index 0eee351b6a..0000000000 --- a/src/soc/amd/stoneyridge/hudson.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) -#include -#endif - - -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - return (int)tmp; -} - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)(PM_MMIO_BASE + reg)); -} - -void hudson_enable(device_t dev) -{ - printk(BIOS_DEBUG, "hudson_enable()\n"); -} - -static void hudson_init_acpi_ports(void) -{ - /* We use some of these ports in SMM regardless of whether or not - * ACPI tables are generated. Enable these ports indiscriminately. - */ - - pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); - pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); - pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); - pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CP00, 6 bytes */ - pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); - - if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { - pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT); - hudson_enable_acpi_cmd_smi(); - } else { - pm_write16(PM_ACPI_SMI_CMD, 0); - } - - /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers - * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn - */ - pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2)); -} - -void hudson_init(void *chip_info) -{ - hudson_init_acpi_ports(); -} - -void hudson_final(void *chip_info) -{ -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) - agesawrapper_fchecfancontrolservice(); -#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) - enable_imc_thermal_zone(); -#endif -#endif -} - -/* - * Update the PCI devices with a valid IRQ number - * that is set in the mainboard PCI_IRQ structures. - */ -static void set_pci_irqs(void *unused) -{ - /* Write PCI_INTR regs 0xC00/0xC01 */ - write_pci_int_table(); - - /* Write IRQs for all devicetree enabled devices */ - write_pci_cfg_irqs(); -} - -/* - * Hook this function into the PCI state machine - * on entry into BS_DEV_ENABLE. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h deleted file mode 100644 index 48f5e0d937..0000000000 --- a/src/soc/amd/stoneyridge/include/soc/hudson.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef STONEYRIDGE_H -#define STONEYRIDGE_H - -#include -#include -#include -#include -#include "chip.h" - -#define IO_APIC2_ADDR 0xfec20000 - -/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ -#define PM_MMIO_BASE 0xfed80300 - -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 - -/* Power management index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 - -#define PM_ACPI_MMIO_EN 0x24 -#define PM_SERIRQ_CONF 0x54 -#define PM_EVT_BLK 0x60 -#define PM1_CNT_BLK 0x62 -#define PM_TMR_BLK 0x64 -#define PM_CPU_CTRL 0x66 -#define PM_GPE0_BLK 0x68 -#define PM_ACPI_SMI_CMD 0x6a -#define PM_ACPI_CONF 0x74 -#define PM_PMIO_DEBUG 0xd2 -#define PM_MANUAL_RESET 0xd3 -#define PM_HUD_SD_FLASH_CTRL 0xe7 -#define PM_YANG_SD_FLASH_CTRL 0xe8 -#define PM_PCIB_CFG 0xea - -#define SYS_RESET 0xcf9 - -#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE -#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ -#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ - -#define ACPI_SMI_CTL_PORT 0xb2 -#define ACPI_SMI_CMD_CST_CONTROL 0xde -#define ACPI_SMI_CMD_PST_CONTROL 0xad -#define ACPI_SMI_CMD_DISABLE 0xbe -#define ACPI_SMI_CMD_ENABLE 0xef -#define ACPI_SMI_CMD_S4_REQ 0xc0 - -#define REV_STONEYRIDGE_A11 0x11 -#define REV_STONEYRIDGE_A12 0x12 - -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define ROUTE_TPM_2_SPI BIT(3) -#define SPI_ROM_ENABLE 0x02 -#define SPI_BASE_ADDRESS 0xfec10000 - -#define LPC_IO_PORT_DECODE_ENABLE 0x44 -#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) -#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) -#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) -#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) -#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) -#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) -#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) -#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) -#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) -#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) -#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) -#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) -#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) -#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) -#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) -#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) -#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) -#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) -#define DECODE_ENABLE_MIDI_PORT0 BIT(18) -#define DECODE_ENABLE_MIDI_PORT1 BIT(19) -#define DECODE_ENABLE_MIDI_PORT2 BIT(20) -#define DECODE_ENABLE_MIDI_PORT3 BIT(21) -#define DECODE_ENABLE_MSS_PORT0 BIT(22) -#define DECODE_ENABLE_MSS_PORT1 BIT(23) -#define DECODE_ENABLE_MSS_PORT2 BIT(24) -#define DECODE_ENABLE_MSS_PORT3 BIT(25) -#define DECODE_ENABLE_FDC_PORT0 BIT(26) -#define DECODE_ENABLE_FDC_PORT1 BIT(27) -#define DECODE_ENABLE_GAME_PORT BIT(28) -#define DECODE_ENABLE_KBC_PORT BIT(29) -#define DECODE_ENABLE_ACPIUC_PORT BIT(30) -#define DECODE_ENABLE_ADLIB_PORT BIT(31) - -#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 -#define LPC_WIDEIO2_ENABLE BIT(25) -#define LPC_WIDEIO1_ENABLE BIT(24) -#define LPC_WIDEIO0_ENABLE BIT(2) - -#define LPC_WIDEIO_GENERIC_PORT 0x64 - -#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 -#define LPC_ALT_WIDEIO2_ENABLE BIT(3) -#define LPC_ALT_WIDEIO1_ENABLE BIT(2) -#define LPC_ALT_WIDEIO0_ENABLE BIT(0) - -#define LPC_WIDEIO2_GENERIC_PORT 0x90 - -#define SPI_CNTRL0 0x00 -#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -/* Nominal is 16.7MHz on older devices, 33MHz on newer */ -#define SPI_READ_MODE_NOM 0x00000000 -#define SPI_READ_MODE_DUAL112 ( BIT(29) ) -#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) -#define SPI_READ_MODE_DUAL122 (BIT(30) ) -#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) -#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) -/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */ -#define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18)) -#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) -#define SPI_ARB_ENABLE BIT(19) - -#define SPI_CNTRL1 0x0c -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ -#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) -#define SPI_NORM_SPEED_SH 12 -#define SPI_FAST_SPEED_SH 8 - -#define SPI100_ENABLE 0x20 -#define SPI_USE_SPI100 BIT(0) - -#define SPI100_SPEED_CONFIG 0x22 -#define SPI_SPEED_66M (0x0) -#define SPI_SPEED_33M ( BIT(0)) -#define SPI_SPEED_22M ( BIT(1) ) -#define SPI_SPEED_16M ( BIT(1) | BIT(0)) -#define SPI_SPEED_100M (BIT(2) ) -#define SPI_SPEED_800K (BIT(2) | BIT(0)) -#define SPI_NORM_SPEED_NEW_SH 12 -#define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 -#define SPI_TPM_SPEED_NEW_SH 0 - -#define SPI100_HOST_PREF_CONFIG 0x2c -#define SPI_RD4DW_EN_HOST BIT(15) - -static inline int hudson_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || - (CONFIG_STONEYRIDGE_SATA_MODE == 2); -} - -static inline int hudson_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || - (CONFIG_STONEYRIDGE_SATA_MODE == 3); -} - -void hudson_enable_rom(void); -void configure_hudson_uart(void); -void hudson_clk_output_48Mhz(void); -void hudson_disable_4dw_burst(void); -void hudson_enable(device_t dev); -void hudson_final(void *chip_info); -void hudson_init(void *chip_info); -void hudson_lpc_port80(void); -void hudson_lpc_decode(void); -void hudson_pci_port80(void); -void hudson_read_mode(u32 mode); -void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void hudson_set_readspeed(u16 norm, u16 fast); -void hudson_tpm_decode_spi(void); -void lpc_wideio_512_window(uint16_t base); -void lpc_wideio_16_window(uint16_t base); -u8 pm_read8(u8 reg); -u16 pm_read16(u16 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -void s3_resume_init_data(void *FchParams); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -void bootblock_fch_early_init(void); - -#endif /* STONEYRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 7a3c804452..193fb0ced3 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -54,12 +54,12 @@ static inline void smi_write16(uint8_t offset, uint16_t value) write16((void *)(SMI_BASE + offset), value); } -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); -void hudson_disable_gevent_smi(uint8_t gevent); -void hudson_enable_acpi_cmd_smi(void); +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void disable_gevent_smi(uint8_t gevent); +void enable_acpi_cmd_smi(void); #ifndef __SMM__ -void hudson_enable_smi_generation(void); +void enable_smi_generation(void); #endif #endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h new file mode 100644 index 0000000000..de481f0eea --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -0,0 +1,207 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef STONEYRIDGE_H +#define STONEYRIDGE_H + +#include +#include +#include +#include +#include "chip.h" + +#define IO_APIC2_ADDR 0xfec20000 + +/* Offsets from ACPI_MMIO_BASE + * This is defined by AGESA, but we don't include AGESA headers to avoid + * polluting the namespace. + */ +#define PM_MMIO_BASE 0xfed80300 + +#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + +/* Power management index/data registers */ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 + +#define PM_ACPI_MMIO_EN 0x24 +#define PM_SERIRQ_CONF 0x54 +#define PM_EVT_BLK 0x60 +#define PM1_CNT_BLK 0x62 +#define PM_TMR_BLK 0x64 +#define PM_CPU_CTRL 0x66 +#define PM_GPE0_BLK 0x68 +#define PM_ACPI_SMI_CMD 0x6a +#define PM_ACPI_CONF 0x74 +#define PM_PMIO_DEBUG 0xd2 +#define PM_MANUAL_RESET 0xd3 +#define PM_HUD_SD_FLASH_CTRL 0xe7 +#define PM_YANG_SD_FLASH_CTRL 0xe8 +#define PM_PCIB_CFG 0xea + +#define SYS_RESET 0xcf9 + +#define STONEYRIDGE_ACPI_IO_BASE CONFIG_STONEYRIDGE_ACPI_IO_BASE +#define ACPI_PM_EVT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PM_TMR_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */ + +#define ACPI_SMI_CTL_PORT 0xb2 +#define ACPI_SMI_CMD_CST_CONTROL 0xde +#define ACPI_SMI_CMD_PST_CONTROL 0xad +#define ACPI_SMI_CMD_DISABLE 0xbe +#define ACPI_SMI_CMD_ENABLE 0xef +#define ACPI_SMI_CMD_S4_REQ 0xc0 + +#define REV_STONEYRIDGE_A11 0x11 +#define REV_STONEYRIDGE_A12 0x12 + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ROM_ENABLE 0x02 +#define SPI_BASE_ADDRESS 0xfec10000 + +#define LPC_IO_PORT_DECODE_ENABLE 0x44 +#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) +#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) +#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) +#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) +#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) +#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) +#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) +#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) +#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) +#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) +#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) +#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) +#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) +#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) +#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) +#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) +#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) +#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) +#define DECODE_ENABLE_MIDI_PORT0 BIT(18) +#define DECODE_ENABLE_MIDI_PORT1 BIT(19) +#define DECODE_ENABLE_MIDI_PORT2 BIT(20) +#define DECODE_ENABLE_MIDI_PORT3 BIT(21) +#define DECODE_ENABLE_MSS_PORT0 BIT(22) +#define DECODE_ENABLE_MSS_PORT1 BIT(23) +#define DECODE_ENABLE_MSS_PORT2 BIT(24) +#define DECODE_ENABLE_MSS_PORT3 BIT(25) +#define DECODE_ENABLE_FDC_PORT0 BIT(26) +#define DECODE_ENABLE_FDC_PORT1 BIT(27) +#define DECODE_ENABLE_GAME_PORT BIT(28) +#define DECODE_ENABLE_KBC_PORT BIT(29) +#define DECODE_ENABLE_ACPIUC_PORT BIT(30) +#define DECODE_ENABLE_ADLIB_PORT BIT(31) + +#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 +#define LPC_WIDEIO2_ENABLE BIT(25) +#define LPC_WIDEIO1_ENABLE BIT(24) +#define LPC_WIDEIO0_ENABLE BIT(2) + +#define LPC_WIDEIO_GENERIC_PORT 0x64 + +#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 +#define LPC_ALT_WIDEIO2_ENABLE BIT(3) +#define LPC_ALT_WIDEIO1_ENABLE BIT(2) +#define LPC_ALT_WIDEIO0_ENABLE BIT(0) + +#define LPC_WIDEIO2_GENERIC_PORT 0x90 + +#define SPI_CNTRL0 0x00 +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +/* Nominal is 16.7MHz on older devices, 33MHz on newer */ +#define SPI_READ_MODE_NOM 0x00000000 +#define SPI_READ_MODE_DUAL112 ( BIT(29) ) +#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) +#define SPI_READ_MODE_DUAL122 (BIT(30) ) +#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) +#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) +#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_ARB_ENABLE BIT(19) + +#define SPI_CNTRL1 0x0c +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) +#define SPI_NORM_SPEED_SH 12 +#define SPI_FAST_SPEED_SH 8 + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +#define SPI100_SPEED_CONFIG 0x22 +#define SPI_SPEED_66M (0x0) +#define SPI_SPEED_33M ( BIT(0)) +#define SPI_SPEED_22M ( BIT(1) ) +#define SPI_SPEED_16M ( BIT(1) | BIT(0)) +#define SPI_SPEED_100M (BIT(2) ) +#define SPI_SPEED_800K (BIT(2) | BIT(0)) +#define SPI_NORM_SPEED_NEW_SH 12 +#define SPI_FAST_SPEED_NEW_SH 8 +#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_TPM_SPEED_NEW_SH 0 + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +static inline int sb_sata_enable(void) +{ + /* True if IDE or AHCI. */ + return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || + (CONFIG_STONEYRIDGE_SATA_MODE == 2); +} + +static inline int sb_ide_enable(void) +{ + /* True if IDE or LEGACY IDE. */ + return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || + (CONFIG_STONEYRIDGE_SATA_MODE == 3); +} + +void sb_enable_rom(void); +void configure_stoneyridge_uart(void); +void sb_clk_output_48Mhz(void); +void sb_disable_4dw_burst(void); +void sb_enable(device_t dev); +void southbridge_final(void *chip_info); +void southbridge_init(void *chip_info); +void sb_lpc_port80(void); +void sb_lpc_decode(void); +void sb_pci_port80(void); +void sb_read_mode(u32 mode); +void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); +void sb_set_readspeed(u16 norm, u16 fast); +void sb_tpm_decode_spi(void); +void lpc_wideio_512_window(uint16_t base); +void lpc_wideio_16_window(uint16_t base); +u8 pm_read8(u8 reg); +u16 pm_read16(u16 reg); +void pm_write8(u8 reg, u8 value); +void pm_write16(u8 reg, u16 value); +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); +void s3_resume_init_data(void *FchParams); +int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +void bootblock_fch_early_init(void); + +#endif /* STONEYRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index fae5c554ba..75cedfe47f 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include @@ -105,7 +105,7 @@ static void lpc_init(device_t dev) pm_write8(PM_SERIRQ_CONF, byte); } -static void hudson_lpc_read_resources(device_t dev) +static void lpc_read_resources(device_t dev) { struct resource *res; global_nvs_t *gnvs; @@ -141,7 +141,7 @@ static void hudson_lpc_read_resources(device_t dev) gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); } -static void hudson_lpc_set_resources(struct device *dev) +static void lpc_set_resources(struct device *dev) { struct resource *res; u32 spi_enable_bits; @@ -162,7 +162,7 @@ static void hudson_lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -static void hudson_lpc_enable_childrens_resources(device_t dev) +static void lpc_enable_childrens_resources(device_t dev) { struct bus *link; u32 reg, reg_x; @@ -218,7 +218,7 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) base = res->base; end = resource_end(res); /* find a resource size */ - printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n", + printk(BIOS_DEBUG, "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n", dev_path(child), base, end); switch (base) { case 0x60: /* KB */ @@ -342,10 +342,10 @@ static void hudson_lpc_enable_childrens_resources(device_t dev) pci_write_config8(dev, 0x74, wiosize); } -static void hudson_lpc_enable_resources(device_t dev) +static void lpc_enable_resources(device_t dev) { pci_dev_enable_resources(dev); - hudson_lpc_enable_childrens_resources(dev); + lpc_enable_childrens_resources(dev); } unsigned long acpi_fill_mcfg(unsigned long current) @@ -359,9 +359,9 @@ static struct pci_operations lops_pci = { }; static struct device_operations lpc_ops = { - .read_resources = hudson_lpc_read_resources, - .set_resources = hudson_lpc_set_resources, - .enable_resources = hudson_lpc_enable_resources, + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 85530256e9..73f944d3aa 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -18,7 +18,7 @@ #include #include -#include +#include #define HT_INIT_CONTROL 0x6c #define HTIC_BIOSR_Detect (1 << 5) diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 1380fb7672..c69bbf6403 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include asmlinkage void car_stage_entry(void) diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index bd013c895d..e2de3e6fdf 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include static void sata_init(struct device *dev) diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 421151af97..0c31a3ed8e 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #define NMI_OFF 0 @@ -37,8 +37,8 @@ #endif /* -* HUDSON enables all USB controllers by default in SMBUS Control. -* HUDSON enables SATA by default in SMBUS Control. +* The southbridge enables all USB controllers by default in SMBUS Control. +* The southbridge enables SATA by default in SMBUS Control. */ static void sm_init(device_t dev) @@ -108,11 +108,11 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void hudson_sm_read_resources(device_t dev) +static void sm_read_resources(device_t dev) { } -static void hudson_sm_set_resources(struct device *dev) +static void sm_set_resources(struct device *dev) { } @@ -120,8 +120,8 @@ static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations smbus_ops = { - .read_resources = hudson_sm_read_resources, - .set_resources = hudson_sm_set_resources, + .read_resources = sm_read_resources, + .set_resources = sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, .scan_bus = scan_smbus, diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 73e67024c8..6669ccba94 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include /*----------------------------------------------------------------------------- @@ -144,7 +144,7 @@ static void setupFch(int ioBase) __outbyte(ioBase + 0x0e, 66000000 / 400000 / 4); } -int hudson_readSpd(int spdAddress, char *buf, size_t len) +int sb_readSpd(int spdAddress, char *buf, size_t len) { int ioBase = 0xb00; setupFch(ioBase); diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index c92697cf6d..31ca5d1da9 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -17,7 +17,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) } /** Set the EOS bit and enable SMI generation from southbridge */ -void hudson_enable_smi_generation(void) +void enable_smi_generation(void) { uint32_t reg = smi_read32(SMI_REG_SMITRIG0); reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index fecaf90723..822738ca27 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -39,7 +39,7 @@ static void configure_smi(uint8_t smi_num, uint8_t mode) * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. * @param level SMI_LVL_LOW or SMI_LVL_HIGH */ -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) { uint32_t reg32; /* GEVENT pins range from [0:23] */ @@ -59,7 +59,7 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) } /** Disable events from given GEVENT pin */ -void hudson_disable_gevent_smi(uint8_t gevent) +void disable_gevent_smi(uint8_t gevent) { /* GEVENT pins range from [0:23] */ if (gevent > 23) { @@ -72,7 +72,7 @@ void hudson_disable_gevent_smi(uint8_t gevent) } /** Enable SMIs on writes to ACPI SMI command port */ -void hudson_enable_acpi_cmd_smi(void) +void enable_acpi_cmd_smi(void) { configure_smi(STONEYRIDGE_SMI_ACPI_COMMAND, SMI_MODE_SMI); } diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 5a646a69f2..a8ff96a3e1 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -9,9 +9,8 @@ #include #include #include -#include #include - +#include #define SMI_0x88_ACPI_COMMAND (1 << 11) @@ -25,7 +24,7 @@ enum smi_source { SMI_SOURCE_0x90 = (1 << 5) }; -static void hudson_apmc_smi_handler(void) +static void sb_apmc_smi_handler(void) { u32 reg32; const uint8_t cmd = inb(ACPI_SMI_CTL_PORT); @@ -88,7 +87,7 @@ static void process_smi_0x88(void) if (status & SMI_0x88_ACPI_COMMAND) { /* Command received via ACPI SMI command port */ - hudson_apmc_smi_handler(); + sb_apmc_smi_handler(); } /* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x88, status); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c new file mode 100644 index 0000000000..5e36100281 --- /dev/null +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) +#include +#endif + + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +void pm_write8(u8 reg, u8 value) +{ + write8((void *)(PM_MMIO_BASE + reg), value); +} + +u8 pm_read8(u8 reg) +{ + return read8((void *)(PM_MMIO_BASE + reg)); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)(PM_MMIO_BASE + reg), value); +} + +u16 pm_read16(u16 reg) +{ + return read16((void *)(PM_MMIO_BASE + reg)); +} + +void sb_enable(device_t dev) +{ + printk(BIOS_DEBUG, "%s\n", __func__); +} + +static void sb_init_acpi_ports(void) +{ + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); + pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); + pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); + pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + /* CpuControl is in \_PR.CP00, 6 bytes */ + pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + pm_write16(PM_ACPI_SMI_CMD, ACPI_SMI_CTL_PORT); + enable_acpi_cmd_smi(); + } else { + pm_write16(PM_ACPI_SMI_CMD, 0); + } + + /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers + * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn + */ + pm_write8(PM_ACPI_CONF, BIT(0) | BIT(1) | BIT(4) | BIT(2)); +} + +void southbridge_init(void *chip_info) +{ + sb_init_acpi_ports(); +} + +void southbridge_final(void *chip_info) +{ +#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) + agesawrapper_fchecfancontrolservice(); +#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) + enable_imc_thermal_zone(); +#endif +#endif +} + +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 7919207175..9cc0c94894 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -14,7 +14,7 @@ */ #include -#include +#include uintptr_t uart_platform_base(int idx) { diff --git a/src/soc/amd/stoneyridge/usb.c b/src/soc/amd/stoneyridge/usb.c index 6f273952cf..c1caf7db4c 100644 --- a/src/soc/amd/stoneyridge/usb.c +++ b/src/soc/amd/stoneyridge/usb.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, -- cgit v1.2.3