From 7ac2af32f317c99be61c94c082cfa411b5e7c144 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 19 Sep 2017 16:26:34 -0600 Subject: amd/stoneyridge: Make UMA memory cacheable Use reserved_ram_resource to help ensure the UMA memory is typed as WB. BUG=b:65856868 TEST=Inspect MTRRs and compare with UMA memory Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/21606 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/northbridge.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/soc/amd') diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 16cda01cf2..049bcd0674 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -484,7 +484,14 @@ void domain_set_resources(device_t dev) " limitk=%08llx\n", mmio_basek, basek, limitk); } - add_uma_resource_below_tolm(dev, 7); + /* UMA is not set up yet, but infer the base & size to make cacheable */ + uint32_t uma_base = restore_top_of_low_cacheable(); + if (uma_base != bsp_topmem()) { + uint32_t uma_size = bsp_topmem() - uma_base; + printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", + __func__, uma_size, uma_base); + reserved_ram_resource(dev, 7, uma_base / KiB, uma_size / KiB); + } for (link = dev->link_list ; link ; link = link->next) if (link->children) -- cgit v1.2.3