From aecca7592b65f68bb45075e3f13af97676463ef6 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 8 Feb 2021 22:14:17 +0100 Subject: soc/amd/stoneyridge/cpu: use MSR_PSP_ADDR define instead of hex number Signed-off-by: Felix Held Change-Id: Id9042def0f5e9d2fa994d6729c592c7e2152976b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50405 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/stoneyridge/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/soc/amd') diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index c898ff7f93..9992fc54aa 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * MP and SMM loading initialization. @@ -121,10 +122,10 @@ static void model_15_init(struct device *dev) uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */ psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4); psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - psp_msr = rdmsr(0xc00110a2); + psp_msr = rdmsr(MSR_PSP_ADDR); if (psp_msr.lo == 0) { psp_msr.lo = psp_bar; - wrmsr(0xc00110a2, psp_msr); + wrmsr(MSR_PSP_ADDR, psp_msr); } } -- cgit v1.2.3