From ef73cb88dc52dbe9ea5cc23939e109e0a7967e89 Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Tue, 19 Jun 2018 07:40:18 -0700 Subject: soc/amd/stoneyridge/southbridge.c: Fix get_index_bit limit check Limit is the maximum number of bits to be tested, however it's being checked against the number of bytes of uint32_t. when it should be number of bits. Create a macro to provide the number of bits, and use it instead of sizeof. BUG=b:75996437 TEST=Add debug messages to see code passing beyond the check, build and boot grunt, check that it passed the limit check, remove debug code. Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/27162 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 + src/soc/amd/stoneyridge/southbridge.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/amd') diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 3e70c32c25..06ef898ca5 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -355,6 +355,7 @@ #define PM1_LIMIT 16 #define GPE0_LIMIT 28 +#define TOTAL_BITS(a) (8 * sizeof(a)) /* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */ #define GPP_CLK_CNTRL 0 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 91435ad42b..c46bcb44a6 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -696,7 +696,7 @@ static int get_index_bit(uint32_t value, uint16_t limit) uint16_t i; uint32_t t; - if (limit >= sizeof(uint32_t)) + if (limit >= TOTAL_BITS(uint32_t)) return -1; /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ -- cgit v1.2.3