From 340e4b80904feb6c5c21497fc52966854fa5ee79 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 23 Oct 2019 17:25:58 +0200 Subject: lib/cbmem_top: Add a common cbmem_top implementation This adds a common cbmem_top implementation to all coreboot target. In romstage a static variable will be used to cache the result of cbmem_top_romstage. In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable needs to be populated by the stage entry with the value passed via the calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the same implementation as will be used as in romstage. Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/cavium/cn81xx/cbmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/cavium/cn81xx') diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index bb6fa18f20..a39bf4fe35 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -20,7 +20,7 @@ #include #include -void *cbmem_top(void) +void *cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); -- cgit v1.2.3