From 90d12351fd5c3626edd283aafe20b2a427f9d344 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Wed, 15 Jul 2015 12:10:05 +0100 Subject: mainboard/google/urara: change SYS PLL to 700MHz This requires changes the interface that sets up the system PLL to support a given reference devider value and given feedback value. Also, this requires a change in the dividers used for UART, USB, I2C setup. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu Reviewed-on: https://review.coreboot.org/12765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/imgtec/pistachio/include/soc/clocks.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/imgtec/pistachio/include') diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index f351a6f9c3..fc07f0aa2d 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -21,7 +21,7 @@ #include /* Functions for PLL setting */ -int sys_pll_setup(u8 divider1, u8 divider2); +int sys_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); /* Peripheral divider setting */ -- cgit v1.2.3