From b9d961550ce07951b472ae558281e288413ab445 Mon Sep 17 00:00:00 2001
From: Ionela Voinescu <ionela.voinescu@imgtec.com>
Date: Fri, 12 Dec 2014 13:53:22 +0000
Subject: urara: add support for DMA coherent memory area

The information about the DMA memory area is further passed
through the coreboot table to the payload.

BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA; DMA memory area was used to test the
     functionality of the DWC2 USB controller driver; behavior was
     as expected.
BRANCH=none

Change-Id: I658e32352bd5fab493ffe15ad9340e19d02fd133
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0debc105b072a37e2a8ae4098a9634d841191d0a
Original-Change-Id: Icf69835dc6a385a59d30092be4ac69bc80245336
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/235910
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9593
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/imgtec/pistachio')

diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 1c7ea9a74c..c3c6c07ebf 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -36,4 +36,6 @@ SECTIONS
 
 	/* Let's use SRAM for CBFS cache. */
 	CBFS_CACHE(0x9b000000, 64K)
+	/* DMA coherent area: end of available DRAM, uncached */
+	DMA_COHERENT(0xAFF00000, 1M)
 }
-- 
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