From fb3ea74f9a1cf6a1e8fa32466457889c965f45ab Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Mon, 8 Dec 2014 12:51:09 +0000 Subject: pistachio: increase the size of romstage to 36K This is necessary for the subsequent changes that will add to the size of romstage. BUG=chrome-os-partner:31438 TEST=coreboot builds successfully;tested on Pistachio FPGA BRANCH=none Change-Id: I132215bd44708913d878bbd8b6147bef535b52df Signed-off-by: Stefan Reinauer Original-Commit-Id: 00f73f9d80a36fc43735f093365564b9d74ed7f7 Original-Change-Id: Ie858416a1c9ab63cfe85eea40a76a093cbd2c79c Original-Signed-off-by: Ionela Voinescu Original-Reviewed-on: https://chromium-review.googlesource.com/233871 Original-Reviewed-by: David Hendricks Original-Commit-Queue: Vadim Bendebury Original-Tested-by: Vadim Bendebury Reviewed-on: http://review.coreboot.org/9589 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/imgtec/pistachio') diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 554ebfc04f..1c7ea9a74c 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -29,7 +29,7 @@ SECTIONS /* GRAM becomes the SRAM. */ SRAM_START(0x9a000000) BOOTBLOCK(0x9a000000, 16K) - ROMSTAGE(0x9a004000, 32K) + ROMSTAGE(0x9a004000, 36K) STACK(0x9a01c000, 8K) PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K) SRAM_END(0x9a020000) -- cgit v1.2.3