From 7100cf2b404887e4f196286e72232153ba3f0524 Mon Sep 17 00:00:00 2001 From: Ionela Voinescu Date: Fri, 24 Jul 2015 14:29:06 +0100 Subject: imgtec/pistachio: Add SOC_REGISTERS memory region When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/imgtec') diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index edf9c41493..a0b48b2e6d 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -29,6 +29,8 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00200000, 512K) RAMSTAGE(0x00280000, 128K) + /* 0x18100000 -> 0x18540000 */ + SOC_REGISTERS(0x18100000, 0x440000) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock * and then through the identity mapping in ROM stage. -- cgit v1.2.3