From 433659ad1e864808ec30e90a62ecfd711559c5a9 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 12 May 2014 21:55:00 -0600 Subject: fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chip While similar to the Bay Trail-M/D code based on the MRC, there are many differences as well: - Obviously, uses the FSP instead of the MRC binaries. - FSP does additional hardware setup, so coreboot doesn't need to. - Different microcode & microcode loading method - Uses the cache_as_ram.inc from the FSP Driver - Various other changes in support of the FSP Additional changes that don't have to to with the FSP vs MRC: - Updated IRQ Routing - Different FADT implementation. This was validated with FSP: BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5 MD5: 9360cd915f0d3e4116bbc782233d7b91 Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4 Signed-off-by: Martin Roth Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/5791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/Kconfig') diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 07099b32b6..3ddbf2841e 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -1 +1,2 @@ source src/soc/intel/baytrail/Kconfig +source src/soc/intel/fsp_baytrail/Kconfig -- cgit v1.2.3