From 4de1a31cb04f0363b6d257d9de392cdfe8d5644c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 15 Jan 2021 05:58:42 +0200 Subject: ACPI: Add acpi_reset_gnvs_for_wake() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/acpi.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/soc/intel/alderlake/acpi.c') diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1536de1f13..2eb6101e0c 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -271,9 +271,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { config_t *config = config_of_soc(); - /* Set unknown wake source */ - gnvs->pm1i = -1; - /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; -- cgit v1.2.3