From ea4ece61b6fc787c652a193ecd04c075daca3158 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sat, 5 Aug 2017 11:12:44 -0700 Subject: soc/intel/apollolake: Enable UART debug controller on S3 resume 1. Add a new variable to GNVS to store information during S3 suspend whether UART debug controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helper functions required by intel/common UARRT driver for enabling controller on S3 resume. BUG=b:64030366 Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/20888 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/apollolake/Makefile.inc') diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 07bbdcdc65..589b846012 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -42,6 +42,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += spi.c smm-y += uart_early.c +smm-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c -- cgit v1.2.3