From c1526f045828a75fecb947c9909792d9b20f187b Mon Sep 17 00:00:00 2001
From: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Date: Mon, 2 May 2016 14:31:04 -0700
Subject: Revert "soc/intel/apollolake: Enable LPC bus interface"

This reverts commit e976bd44692d2adb320a1256f1b6bfaa6469108a.

The LPC resource allocation will be completely reworked in subsequent
patches. The most straightforward approach is to start by reverting
the existing code.

Change-Id: I2475542b79817020d4c956f22ed5856f05046b16
Reviewed-on: https://review.coreboot.org/14583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/apollolake/bootblock/bootblock.c | 28 --------------------------
 1 file changed, 28 deletions(-)

(limited to 'src/soc/intel/apollolake/bootblock')

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index abb713e708..833f531936 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -22,7 +22,6 @@
 #include <soc/bootblock.h>
 #include <soc/cpu.h>
 #include <soc/gpio.h>
-#include <soc/lpc.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
 #include <soc/uart.h>
@@ -31,36 +30,12 @@ static const struct pad_config tpm_spi_configs[] = {
 	PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3),	/* FST_SPI_CS2_N */
 };
 
-static const struct pad_config lpc_gpio_configs[] = {
-	PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
-	PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
-	PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
-};
-
 static void tpm_enable(void)
 {
 	/* Configure gpios */
 	gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs));
 }
 
-static void early_lpc_enable(void)
-{
-	/* Enable requested fixed IO decode ranges */
-	pci_write_config16(LPC_DEV, LPC_EN, LPC_EN_MC1 | LPC_EN_KB | LPC_EN_LGAME);
-
-	/* Enable generic IO decode ranges for 0x800-0x9ff */
-	/* FIXME: remove range hardcoding and/or calculate based on EC definitions */
-	pci_write_config32(LPC_DEV, LPC_GEN1_DEC, ((0xff & ~3 ) << 8) | 0x800 | 1);
-	pci_write_config32(LPC_DEV, LPC_GEN2_DEC, ((0xff & ~3 ) << 8) | 0x900 | 1);
-
-	/* GPIO pins need to be configured to specific native function */
-	gpio_configure_pads(lpc_gpio_configs, ARRAY_SIZE(lpc_gpio_configs));
-}
-
 void asmlinkage bootblock_c_entry(void)
 {
 	device_t dev = NB_DEV_ROOT;
@@ -105,8 +80,5 @@ void bootblock_soc_early_init(void)
 	if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
 		tpm_enable();
 
-	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC))
-		early_lpc_enable();
-
 	cache_bios_region();
 }
-- 
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