From 8885529e15cfa4b01a7678663d2eda9695bb8cfc Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 27 Nov 2018 15:13:22 +0100 Subject: soc/intel/apl: Configure LPC serial IRQ mode Sync the FSP settings with what coreboot does. Why both FSP and coreboot configure this redundantly stays a secret. TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC works correctly now, but was confused by the wrong settings before because the FSP defaults allowed to disable the LPC clock. Change-Id: Id1c7180f460678bf0f9458228591050dd628c052 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/29901 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Werner Zeh --- src/soc/intel/apollolake/chip.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/soc/intel/apollolake/chip.c') diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 85fe30c7ca..1c8f321924 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -609,6 +609,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + switch (cfg->serirq_mode) { + case SERIRQ_QUIET: + silconfig->SirqEnable = 1; + silconfig->SirqMode = 0; + break; + case SERIRQ_CONTINUOUS: + silconfig->SirqEnable = 1; + silconfig->SirqMode = 1; + break; + case SERIRQ_OFF: + default: + silconfig->SirqEnable = 0; + break; + } + if (cfg->emmc_tx_cmd_cntl != 0) silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; if (cfg->emmc_tx_data_cntl1 != 0) -- cgit v1.2.3