From 9d490daf8d8327f8f01123cf152edf75474f54ce Mon Sep 17 00:00:00 2001
From: Kane Chen <kane.chen@intel.com>
Date: Wed, 11 Jan 2017 12:53:58 +0800
Subject: soc/intel/apollolake: Allow USB2 eye pattern configuration in
 devicetree

This code allows people to override the usb2 eye pattern
UPD settings for boards.

BUG=chrome-os-partner:61031
BRANCH=None
TEST=Usb2 function ok and make sure fsp upd is overridden

Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/18060
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/apollolake/chip.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/soc/intel/apollolake/chip.h')

diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 5f8fed9a56..d60ffbf9f6 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -24,6 +24,7 @@
 #include <soc/intel/common/lpss_i2c.h>
 #include <device/i2c.h>
 #include <soc/pm.h>
+#include <soc/usb.h>
 
 #define CLKREQ_DISABLED		0xf
 #define APOLLOLAKE_I2C_DEV_MAX	8
@@ -115,6 +116,10 @@ struct soc_intel_apollolake_config {
 
 	/* GPIO pin for PERST_0 */
 	uint16_t prt0_gpio;
+
+	/* USB2 eye diagram settings per port */
+	struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX];
+
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */
-- 
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