From 0be3da53c6eb1b4c05a51151c8059fbb4d4024ac Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 19 Jun 2016 23:20:43 -0700 Subject: intel/apollolake: Calculate BIOS mmap at runtime Instead of hard-coding the BIOS region start and end addresses, read BIOS_BFPREG to determine the base and limit for the mapped BIOS region. BUG=chrome-os-partner:54563 Change-Id: Iddd3d4cc945f09e8f147e293bb9144471a6a220d Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/15269 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/include/soc/spi.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/apollolake/include') diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h index f67110f125..20e78d7843 100644 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ b/src/soc/intel/apollolake/include/soc/spi.h @@ -28,12 +28,19 @@ #define SPIBAR_BIOS_CONTROL_EISS (1 << 5) /* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ +#define SPIBAR_BIOS_BFPREG 0x00 #define SPIBAR_HSFSTS_CTL 0x04 #define SPIBAR_FADDR 0x08 #define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) #define SPIBAR_PTINX 0xcc #define SPIBAR_PTDATA 0xd0 +/* Bit definitions and masks for BIOS_BFPREG register. */ +#define SPIBAR_BFPREG_PRB_MASK (0x7fff) +#define SPIBAR_BFPREG_PRL_SHIFT (16) +#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) +#define SPIBAR_BFPREG_SBRS (1 << 31) + /* Bit definitions for HSFSTS_CTL register */ #define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) #define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) -- cgit v1.2.3