From 4bc6edf90956a9971aedb187e570d5c0f58d70cd Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Tue, 29 Aug 2017 14:11:16 -0700 Subject: soc/intel/apollolake: Add PrmrrSize and SGX enable config Add PrmrrSize and sgx_enable config option. PrmrrSize gets configured in romstage so that FSP can allocate memory for SGX. Also, adjust cbmem_top() calculation. Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e Signed-off-by: Pratik Prajapati Reviewed-on: https://review.coreboot.org/21274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Subrata Banik --- src/soc/intel/apollolake/memmap.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/apollolake/memmap.c') diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index f9a484a7c4..6d68501162 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -26,6 +26,7 @@ #include #include #include +#include "chip.h" #include #include #include @@ -34,7 +35,25 @@ void *cbmem_top(void) { - return (void *)sa_get_tseg_base(); + const struct device *dev; + const config_t *config; + void *tolum = (void *)sa_get_tseg_base(); + + if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) + return tolum; + + dev = dev_find_slot(0, PCH_DEVFN_LPC); + assert(dev != NULL); + config = dev->chip_info; + + if (!config) + die("Failed to get chip_info\n"); + + /* FSP allocates 2x PRMRR Size Memory for alignment */ + if (config->sgx_enable) + tolum -= config->PrmrrSize * 2; + + return tolum; } int smm_subregion(int sub, void **start, size_t *size) -- cgit v1.2.3