From 41cfd5ba69783c33883d4515ffa15ac279afb831 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 6 Dec 2017 11:22:53 -0800 Subject: soc/intel/apollolake: Add SMI and SCI support for ESPI This patch adds the SMI bits for SMI_EN, SMI_STS and GPE register in pm.h. The southbridge handler for espi smi is also added. In gpe.h we add GPE0A_ESPI_SCI_STS which is bit 20 in GPE register and enables the setting of the ESPI_SCI STS bit to generate a wake event and/or an SCI/SMI. TEST= Boot to OS. Change-Id: I2b8372ffbe0949ddd4aa83bdd7c0a01ade3ed40e Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/22758 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/smihandler.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/apollolake/smihandler.c') diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index 22c793051d..37d63a1ba5 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -41,4 +41,7 @@ const smi_handler_t southbridge_smi[32] = { [GPIO_SMI_STS] = smihandler_southbridge_gpi, [TCO_SMI_STS] = smihandler_southbridge_tco, [PERIODIC_SMI_STS] = smihandler_southbridge_periodic, +#if IS_ENABLED(CONFIG_SOC_ESPI) + [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, +#endif }; -- cgit v1.2.3