From 0c85b7f4d7180c9307fd95bb887791d4231397a5 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Sat, 23 Apr 2016 12:31:01 -0700 Subject: soc/intel/apollolake: Add cache for BIOS ROM Enable caching of BIOS region with variable MTRR. This is most useful if enabled early such as in bootblock. Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/14480 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/bootblock/bootblock.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/soc/intel/apollolake') diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index bb3b9c10e9..245645518a 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -16,7 +16,9 @@ */ #include #include +#include #include +#include #include #include #include @@ -76,6 +78,24 @@ void asmlinkage bootblock_c_entry(void) main(); } +static void cache_bios_region(void) +{ + int mtrr; + uint32_t rom_size, alignment; + + mtrr = get_free_var_mtrr(); + + if (mtrr==-1) + return; + + /* Only the IFD BIOS region is memory mapped (at top of 4G) */ + rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START; + /* Round to power of two */ + alignment = 1 << (log2_ceil(rom_size)); + rom_size = ALIGN_UP(rom_size, alignment); + set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); +} + void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ @@ -88,4 +108,5 @@ void bootblock_soc_early_init(void) if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)) early_lpc_enable(); + cache_bios_region(); } -- cgit v1.2.3