From d8c4f2b72462f60ae92a59a976437c2407ec6654 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 22 Apr 2014 10:46:06 -0700 Subject: baytrail: Move MRC cache code to a common directory This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/soc/intel/baytrail/Makefile.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/soc/intel/baytrail/Makefile.inc') diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index ce1f2433bb..f5c4c9f6e7 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,7 @@ subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage +subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -13,9 +14,6 @@ romstage-y += memmap.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c -ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c -ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-y += spi.c smm-y += spi.c ramstage-y += chip.c -- cgit v1.2.3