From 8cbf47f12cfbf4ef8130b3e91bc1b29044238af5 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 4 Dec 2013 11:03:20 -0600 Subject: baytrail: add lpe codec clock configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device tree option to determine if the LPE audio codec has a platform clock signal connected to it from the SoC. If a frequency is selected the platform clock number is used to enable the clock. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted rambi with 25MHz option. Probed pin to audio codec. Noted 25MHz clock. Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/178780 Reviewed-by: Shawn Nematbakhsh Reviewed-on: http://review.coreboot.org/4986 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/chip.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/baytrail/chip.h') diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 4c8897c752..250f644cac 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -47,6 +47,10 @@ struct soc_intel_baytrail_config { uint32_t usb2_per_port_rcomp_hs_pullup2; uint32_t usb2_per_port_lane3; uint32_t usb2_per_port_rcomp_hs_pullup3; + + /* LPE Audio Clock configuration. */ + int lpe_codec_clk_freq; /* 19 or 25 are valid. */ + int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ }; extern struct chip_operations soc_intel_baytrail_ops; -- cgit v1.2.3