From b40e444aee50c4b9768b596f0d7cf726f8d2c10f Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 9 Dec 2013 14:38:57 -0800 Subject: baytrail: Enable panel and set timings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These need to be set before the kernel will work without running the VBIOS option rom. Also necessary is setting the PP_CONTROL register with the EDP_FORCE_VDD bit. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/179364 Reviewed-by: Aaron Durbin Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/5000 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/chip.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'src/soc/intel/baytrail/chip.h') diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 43a3efb650..2cc3fd65e3 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -55,6 +55,31 @@ struct soc_intel_baytrail_config { /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; uint32_t sdcard_cap_high; + + /* + * Digital Port Hotplug Enable: + * 0x04 = Enabled, 2ms short pulse + * 0x05 = Enabled, 4.5ms short pulse + * 0x06 = Enabled, 6ms short pulse + * 0x07 = Enabled, 100ms short pulse + */ + int gpu_pipea_hotplug; + int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipea_power_on_delay; + uint16_t gpu_pipea_light_on_delay; + uint16_t gpu_pipea_power_off_delay; + uint16_t gpu_pipea_light_off_delay; + uint16_t gpu_pipea_power_cycle_delay; + uint32_t gpu_pipea_backlight_pwm; + + int gpu_pipeb_hotplug; + int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipeb_power_on_delay; + uint16_t gpu_pipeb_light_on_delay; + uint16_t gpu_pipeb_power_off_delay; + uint16_t gpu_pipeb_light_off_delay; + uint16_t gpu_pipeb_power_cycle_delay; + uint32_t gpu_pipeb_backlight_pwm; }; extern struct chip_operations soc_intel_baytrail_ops; -- cgit v1.2.3