From ba9b7bfc6f4b6622fa2d272faeb32b7135287ee6 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Sat, 17 Jan 2015 08:19:54 +0800 Subject: baytrail: add code for supporting 2x ddr refresh rate this code change provides a way to enable 2x refresh rate in RW image In baytrail, it enables 2x refresh rate by default BUG=chrome-os-partner:35210 BRANCH=none TEST=check the register is set properly on rambi Change-Id: I2a935b570c564986898b6c2064fc7ad43506dcba Signed-off-by: Stefan Reinauer Original-Commit-Id: c740d403708862514be9fa24f56b2764328979eb Original-Change-Id: I84f33d75ea7ebfea180b304e8ff683884f0dbe8a Original-Signed-off-by: Kane Chen Original-Reviewed-on: https://chromium-review.googlesource.com/241754 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9498 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/baytrail/chip.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/baytrail/chip.h') diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 97b92efb99..ecf1ce3da9 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -88,6 +88,7 @@ struct soc_intel_baytrail_config { uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_power_cycle_delay; int gpu_pipeb_pwm_freq_hz; + int disable_ddr_2x_refresh_rate; }; extern struct chip_operations soc_intel_baytrail_ops; -- cgit v1.2.3